Nexperia

74LVC2GU04

Dual unbuffered inverter

VEXT

VCC

VI

VO

mna616

DUT

CL

RT

RL

RL

G

Test data is given in Table 10.

Definitions for test circuit:

RL = Load resistance;

CL = Load capacitance including jig and probe capacitance;

RT = Termination resistance should be equal to the output impedance Zo of the pulse generator;

VEXT = External voltage for measuring switching times.

Fig. 8. Test circuit for measuring switching times

Table 10. Test data

Supply voltage

Input

Load

VEXT

VCC

VI

tr = tf

CL

RL

tPLH, tPHL

1.65 V to 1.95 V

VCC

≤ 2.0 ns

30 pF

1 kΩ

open

2.3 V to 2.7 V

VCC

≤ 2.0 ns

30 pF

500 Ω

open

2.7 V

2.7 V

≤ 2.5 ns

50 pF

500 Ω

open

3.0 V to 3.6 V

2.7 V

≤ 2.5 ns

50 pF

500 Ω

open

4.5 V to 5.5 V

VCC

≤ 2.5 ns

50 pF

500 Ω

open

0

2

1

3

5

6

VCC (V)

160

120

40

0

80

4

gfs

(mA/V)

mnb108

Tamb = 25 °C.

Fig. 9. Typical forward transconductance as a function

of supply voltage

mna638

VCC

Rbias = 560 kΩ

input

0.47 µF

100 µF

output

A IO

VI

fi = 1 kHz.

VO is constant.

Fig. 10. Test set-up for measuring forward

transconductance

74LVC2GU04

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© Nexperia B.V. 2022. All rights reserved

Product data sheet

Rev. 13 — 20 January 2022

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