Nexperia

74LVC02A

Quad 2-input NOR gate

4. Functional diagram

mna216

1A

1B

1Y

3

2

1

2A

2B

2Y

6

5

4

3A

3B

3Y

9

8

10

4A

4B

4Y

12

11

13

Fig. 1. Logic symbol

mna217

1

1

1

1

1

3

2

4

6

5

10

9

8

13

12

11

Fig. 2. IEC logic symbol

mna215

A

B

Y

Fig. 3. Logic diagram (one gate)

5. Pinning information

5.1. Pinning

74LVC02A

1Y

VCC

1A

4Y

1B

4B

2Y

4A

2A

3Y

2B

3B

GND

3A

001aac919

1

2

3

4

5

6

7

8

10

9

12

11

14

13

Fig. 4. Pin configuration for SOT108-1 (SO14) and

SOT402-1 (TSSOP14)

001aac920

74LVC02A

Transparent top view

2B

3B

2A

3Y

2Y

4A

1B

4B

1A

4Y

6

9

5

10

4

11

3

12

2

13

terminal 1

index area

GND(1)

(1) This is not a ground pin. There is no electrical or

mechanical requirement to solder the pad. In case

soldered, the solder land should remain floating or

connected to GND.

Fig. 5. Pin configuration for SOT762-1 (DHVQFN14)

5.2. Pin description

Table 2. Pin description

Symbol

Pin

Description

1Y to 4Y

1, 4, 10, 13

data output

1A to 4A

2, 5, 8, 11

data input

1B to 4B

3, 6, 9,12

data input

GND

7

ground (0 V)

VCC

14

supply voltage

74LVC02A

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 10 — 17 September 2021

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