Timing Diagrams

TLF9547 – 5

j

With XTR HIGH the rising edge of CP loads data from the latches to the counter

k

With XTR LOW the rising edge of CP begins count-down cycle

l

When the count reaches zero Q goes HIGH and Q2 toggles state

m

The next occurrence of XTR clears Q

FIGURE 1 MODE 0 and MODE 1 (Inverse Output of Mode 0)

TLF9547 – 6

j

With XTR HIGH the rising edge of CP loads data from the latches to the counter

k

With XTR LOW the rising edge of CP begins the count-down cycle

l

When the count reaches zero Q goes HIGH for one period of CP and Q2 toggles state

FIGURE 2 MODE 2 and MODE 3 (Inverse Output of Mode 2)

TLF9547 – 7

FIGURE 3 MODE 4 and MODE 5

j

With XTR HIGH the rising edge of CP loads data from the latches into the counter

k

With XTR LOW the rising edge of CP begins the count-down

l

With XTR HIGH during count-down the rising edge of CP does nothing

m

When the count reaches zero Q goes HIGH for one clock cycle and Q2 toggles state

Note

Once the count reaches zero the counter can be reloaded with XTR HIGH

4