P87LPC764HDH datasheet(10/60 Pages) PHILIPS

10 / 60 page

Philips Semiconductors

Product data

P87LPC764

Low power, low price, low pin count (20 pin)

microcontroller with 4 kbyte OTP

2003 Sep 03

FUNCTIONAL DESCRIPTION

Details of P87LPC764 functions will be described in the following

sections.

Enhanced CPU

The P87LPC764 uses an enhanced 80C51 CPU which runs at twice

the speed of standard 80C51 devices. This means that the

performance of the P87LPC764 running at 5 MHz is exactly the same

as that of a standard 80C51 running at 10 MHz. A machine cycle

consists of 6 oscillator cycles, and most instructions execute in 6 or 12

clocks. A user configurable option allows restoring standard 80C51

execution timing. In that case, a machine cycle becomes 12 oscillator

cycles.

In the following sections, the term “CPU clock” is used to refer to the

clock that controls internal instruction execution. This may

sometimes be different from the externally applied clock, as in the

case where the part is configured for standard 80C51 timing by

means of the CLKR configuration bit or in the case where the clock

is divided down via the setting of the DIVM register. These features

are described in the Oscillator section.

Analog Functions

The P87LPC764 incorporates two Analog Comparators. In order to

give the best analog function performance and to minimize power

consumption, pins that are actually being used for analog functions

must have the digital outputs and the digital inputs disabled.

Digital outputs are disabled by putting the port output into the Input

Only (high impedance) mode as described in the I/O Ports section

(see page 17).

Digital inputs on port 0 may be disabled through the use of the

PT0AD register. Each bit in this register corresponds to one pin of

Port 0. Setting the corresponding bit in PT0AD disables that pin’s

digital input. Port bits that have their digital inputs disabled will be

read as 0 by any instruction that accesses the port.

Analog Comparators

Two analog comparators are provided on the P87LPC764. Input and

output options allow use of the comparators in a number of different

configurations. Comparator operation is such that the output is a

logical one (which may be read in a register and/or routed to a pin)

when the positive input (one of two selectable pins) is greater than

the negative input (selectable from a pin or an internal reference

voltage). Otherwise the output is a zero. Each comparator may be

configured to cause an interrupt when the output value changes.

Comparator Configuration

Each comparator has a control register, CMP1 for comparator 1 and

CMP2 for comparator 2. The control registers are identical and are

shown in Figure 2.

The overall connections to both comparators are shown in Figure 3.

There are eight possible configurations for each comparator, as

determined by the control bits in the corresponding CMPn register:

CPn, CNn, and OEn. These configurations are shown in Figure 4.

The comparators function down to a VDD of 3.0V.

When each comparator is first enabled, the comparator output and

interrupt flag are not guaranteed to be stable for 10 microseconds.

The corresponding comparator interrupt should not be enabled

during that time, and the comparator interrupt flag must be cleared

before the interrupt is enabled in order to prevent an immediate

interrupt service.

BIT

SYMBOL

FUNCTION

CMPn.7, 6

—

Reserved for future use. Should not be set to 1 by user programs.

CMPn.5

CEn

Comparator enable. When set by software, the corresponding comparator function is enabled.

Comparator output is stable 10 microseconds after CEn is first set.

CMPn.4

CPn

Comparator positive input select. When 0, CINnA is selected as the positive comparator input. When

1, CINnB is selected as the positive comparator input.

CMPn.3

CNn

Comparator negative input select. When 0, the comparator reference pin CMPREF is selected as

the negative comparator input. When 1, the internal comparator reference Vref is selected as the

negative comparator input.

CMPn.2

OEn

Output enable. When 1, the comparator output is connected to the CMPn pin if the comparator is

enabled (CEn = 1). This output is asynchronous to the CPU clock.

CMPn.1

COn

Comparator output, synchronized to the CPU clock to allow reading by software. Cleared when the

comparator is disabled (CEn = 0).

CMPn.0

CMFn

Comparator interrupt flag. This bit is set by hardware whenever the comparator output COn changes

state. This bit will cause a hardware interrupt if enabled and of sufficient priority. Cleared by

software and when the comparator is disabled (CEn = 0).

CMFn

SU01152

COn

OEn

CNn

CPn

CEn

—

CMPn

Reset Value: 00h

Not Bit Addressable

Address: ACh for CMP1, ADh for CMP2

Figure 2. Comparator Control Registers (CMP1 and CMP2)

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