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AD8134ACP-R2 数据表(PDF) 17 Page - Analog Devices |
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AD8134ACP-R2 数据表(HTML) 17 Page - Analog Devices |
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17 / 20 page ![]() AD8134 Rev. A | Page 17 of 20 –OUT R +OUT R –OUT G +OUT G –OUT B +OUT B VOCM WEIGHTING EQUATIONS: RED VOCM = K(VSYNC – HSYNC) + VMIDSUPPLY GREEN VOCM = K(–2VSYNC) + VMIDSUPPLY BLUE VOCM = K(VSYNC + HSYNC) + VMIDSUPPLY +IN R –IN R VSYNC HSYNC SYNC LEVEL +IN G –IN G +IN B –IN B R 1.5k Ω 1.5k Ω AD8134 750 Ω 750 Ω G 1.5k Ω 1.5k Ω 750 Ω 750 Ω VOCM VOCM VOCM B 1.5k Ω 1.5k Ω 750 Ω 750 Ω OPD ×2 2 2 2 Figure 34. AD8134 Sync-On-Common-Mode Encoding Scheme 0 0.5 1.0 1.5 2.0 4.0 3.5 4.5 2.5 3.0 5.0 0.98 0.99 1.00 1.01 1.03 1.04 1.05 1.02 1.06 1.07 TIME ( μs) HSYNC VSYNC 2.0 2.1 2.2 2.3 2.4 2.9 2.8 3.0 2.5 2.6 2.7 3.1 R G B Figure 35. AD8134 Sync-On-Common-Mode Signals in Single 5 V Application The transmitted common-mode sync signal magnitudes are scaled by applying a dc voltage to the SYNC LEVEL input, referenced to the negative supply. The difference between the voltage applied to the SYNC LEVEL input and the negative supply sets the peak deviation of the encoded sync signals about the midsupply common-mode voltage. For example, with the SYNC LEVEL input set at VS− + 500 mV, the deviation of the encoded sync pulses about the nominal midsupply common- mode voltage is typically ±500 mV. The equations in Figure 34 describe how the VSYNC and HSYNC signals are encoded on each color’s midsupply common-mode signal. In these equations, the weights of the VSYNC and HSYNC signals are ±1 (+1 for high, −1 for low), and the constant K is equal to the peak deviation of the encoded sync signals. Figure 35 shows how the sync signals appear on each common- mode voltage in a single 5 V supply application when the voltage applied to the SYNC LEVEL input is 500 mV. A typical setting for the SYNC LEVEL voltage is 500 mV above the negative supply. LEVEL-SHIFTING SYNC PULSES ON ±5 V SUPPLIES The vertical and horizontal sync pulses received from a computer video port are generally referenced to ground. When using ±5 V supplies, these pulses must be level-shifted before being applied to the negative-supply referenced VSYNC and HSYNC inputs because these inputs are referenced to the negative supply. The circuit shown in Figure 36 provides the proper sync pulse level-shifting for a negative supply voltage of −5 V. The vertical and horizontal sync pulses each require a level-shift circuit. 6.04k Ω 2.21k Ω LEVEL-SHIFTED SYNC PULSE TO AD8134 GROUND-REFERENCED SYNC PULSE 1k Ω VS– 2N3906 Figure 36. Level-Shifting Sync Pulses on ±5 V Supplies |
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