AD8317

Rev. 0 | Page 12 of 20

USING THE AD8317

BASIC CONNECTIONS

The AD8317 is specified for operation up to 10 GHz; as a result,

low impedance supply pins with adequate isolation between

functions are essential. A power supply voltage of between 3.0 V

and 5.5 V should be applied to VPOS. Power supply decoupling

capacitors of 100 pF and 0.1 μF should be connected close to

this power supply pin.

AD8317

1

2

3

4

8

7

6

5

SIGNAL

INPUT

R1

52.3

Ω

R2

0

Ω

R4

0

Ω

C2

C1

C5

C4

47nF

47nF

SEE TEXT

SEE TEXT

0.1

μF

100pF

INHI

INLO

VPOS

TADJ

VOUT

COMM

CLPF

VSET

Figure 22. Basic Connections

The paddle of the LFCSP_VD package is internally connected

to COMM. For optimum thermal and electrical performance,

the paddle should be soldered to a low impedance ground plane.

INPUT SIGNAL COUPLING

The RF input (INHI) is single-ended and must be ac-coupled.

INLO (input common) should be ac-coupled to ground.

Suggested coupling capacitors are 47 nF ceramic 0402-style

capacitors for input frequencies of 1 MHz to 10 GHz. The

coupling capacitors should be mounted close to the INHI and

INLO pins. The coupling capacitor values can be increased to

lower the input stage’s high-pass cutoff frequency. The high-pass

corner is set by the input coupling capacitors and the internal

10 pF high-pass capacitor. The dc voltage on INHI and INLO is

VPOS

2k

Ω

A = 9dB

18.7k

Ω

18.7k

Ω

CURRENT

Gm

STAGE

INLO

INHI

OFFSET

COMP

5pF

5pF

FIRST

GAIN

STAGE

Figure 23. Input Interface

While the input can be reactively matched, in general this is not

necessary. An external 52.3 Ω shunt resistor (connected on the

signal side of the input coupling capacitors, as shown in

Figure 22) combines with the relatively high input impedance

to give an adequate broadband 50 Ω match.

should be as large as possible to minimize the coupling of

unwanted low frequency signals. In low frequency applications,

a simple RC network forming a low-pass filter should be added

at the input for similar reasons. This should generally be placed

at the generator side of the coupling capacitors, thereby

lowering the required capacitance value for a given high-pass

corner frequency.

OUTPUT INTERFACE

The VOUT pin is driven by a PNP output stage. An internal 10 Ω

resistor is placed in series with the output and the VOUT pin.

The rise time of the output is limited mainly by the slew on

CLPF. The fall time is an RC-limited slew given by the load

capacitance and the pull-down resistance at VOUT. There is an

internal pull-down resistor of 1.6 kΩ. A resistive load at VOUT

is placed in parallel with the internal pull-down resistor to

provide additional discharge current.

+

0.8V

1200

Ω

400

Ω

–

10

Ω

VOUT

VPOS

CLPF

COMM

Figure 24. Output Interface

To reduce the fall time, VOUT should be loaded with a resistive

load of <1.6 kΩ. For example, with an external load of 150 Ω the

AD8317 fall time is <7 ns.

SETPOINT INTERFACE

to VSET, the feedback loop forces

The result is