AD9513SLASHPCBZ datasheet(19/28 Pages) AD

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AD9513

Rev. 0 | Page 19 of 28

Table 11. Output Delay Full Scale

Delay

Bypass

1/3

1.8 ns

2/3

6.0 ns

11.6 ns

Table 12. Output Logic Configuration

OUT0

OUT1

OUT2

OFF

LVDS

OFF

1/3

CMOS

OFF

2/3

LVDS

OFF

LVDS

CMOS

OFF

1/3

CMOS

1/3

LVDS

2/3

1/3

LVDS

CMOS

1/3

CMOS

LVDS

2/3

OFF

1/3

2/3

OFF

LVDS

2/3

OFF

CMOS

2/3

OFF

CMOS

OFF

LVDS

OFF

CMOS

1/3

CMOS

OFF

LVDS

2/3

LVDS

OFF

LVDS

CMOS

OFF

CMOS

Table 13. OUT2 Delay or Phase

OUT2

Delay

(S0 ≠ 0)

OUT2

Phase

(S0 = 0)

1/3

1/16

2/3

1/8

3/16

1/3

1/4

1/3

5/16

2/3

1/3

3/8

1/3

7/16

2/3

1/2

1/3

2/3

9/16

2/3

5/8

2/3

11/16

3/4

1/3

13/16

2/3

7/8

15/16

Table 14. OUT2 Divide or OUT1 Phase

OUT2

Divide (Duty Cycle1)

(S2 ≠ 0)

OUT1

Phase

(S2 = 0)

1/3

2 (50%)

2/3

3 (33%)

4 (50%)

1/3

5 (40%)

1/3

6 (50%)

2/3

1/3

8 (50%)

1/3

9 (44%)

2/3

10 (50%)

1/3

2/3

12 (50%)

2/3

15 (47%)

2/3

16 (50%)

18 (50%)

1/3

24 (50%)

2/3

30 (50%)

32 (50%)

1 Duty cycle is the clock signal high time divided by the total period.

Table 15. OUT1 Divide or OUT2 Phase

OUT1

Divide (Duty Cycle1)

(S2 ≠ 1)

OUT2 Phase

(S2 = 1 and S0 ≠ 0)

1/3

2 (50%)

2/3

3 (33%)

4 (50%)

1/3

5 (40%)

1/3

6 (50%)

2/3

1/3

8 (50%)

1/3

9 (44%)

2/3

10 (50%)

1/3

2/3

12 (50%)

2/3

15 (47%)

2/3

16 (50%)

18 (50%)

1/3

24 (50%)

2/3

30 (50%)

32 (50%)

1 Duty cycle is the clock signal high time divided by the total period.

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