AD9882ASLASHPCB datasheet(29/40 Pages) AD

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AD9882A

Rev. 0 | Page 29 of 40

Table 23. Active Vsync Override Settings

Override

Result

Autodetermines the active Vsync

Override; Bit 0 determines the

active Vsync.

The default for this register is 0.

0x10 0

Active Vsync Select

This bit is used to select the active Vsync when the override bit

is set (Bit 1).

Table 24. Active Vsync Select Settings

Select

Result

Vsync input

Sync separator output

The default for this register is 0.

0x11 7

Clamp Function

This bit enables/disables clamping.

Table 25. Clamp Input Signal Source Settings

Clamp Function

Function

Internally generated clamp enabled

Clamping disabled

0 enables the clamp timing circuitry controlled by clamp

placement and clamp duration. The clamp position and

duration is counted from the trailing edge of Hsync.

1 disables clamping. The three channels are clamped when the

clamp signal is active.

Power-up default value for clamp function is 0.

0x11 6

Red Clamp Select

A bit that determines whether the red channel is clamped to

ground or to midscale. For RGB video, all three channels are

referenced to ground. For YPbPr, the Y channel is referenced to

ground, but the PbPr channels are referenced to midscale.

Clamping to midscale clamps to Pin 74.

Table 26. Red Clamp Select Settings

Clamp

Function

Clamp to ground

Clamp to midscale (Pin 74)

The default setting for this register is 0.

0x11 5

Green Clamp Select

This bit determines whether the green channel is clamped to

ground or to midscale.

Table 27. Green Clamp Select Settings

Clamp

Function

Clamp to ground

Clamp to midscale (Pin 74)

The default setting for this register is 0.

0x11 4

Blue Clamp Select

This bit determines whether the blue channel is clamped to

ground or to midscale.

Table 28. Blue Clamp Select Settings

Clamp

Function

Clamp to ground

Clamp to midscale (Pin 74)

The default setting for this register is 0.

0x11 3

Coast Select

This bit is used to enable or disable the coast signal. If coast is

enabled, the additional decision of using the Vsync input pin

or the output from the sync separator needs to be made

(Register 0x10, Bits 1, 0). To disable coast, the user must set

Table 29. Coast Enable Settings

Select

Result

Coast disabled

Internally generated coast signal

The default for this register is 1.

0x11 2

Coast Input Polarity Override

This register is used to override the internal circuitry that

determines the polarity of the coast signal going into the PLL.

When disabling coast, Register 11, Bit 2 must be set to 1 and

when coast is disabled. It does not work with internal coast.

Table 30. Coast Input Polarity Override Settings

Override Bit

Result

Coast polarity determined by chip

Coast polarity determined by user

The default for coast polarity override is 0.

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