BST120 datasheet(2/12 Pages) PHILIPS

部件名	BST120

功能描述	P-channel enhancement mode vertical D-MOS transistor

PDF	12 Pages

Scroll/Zoom	100%

制造商	PHILIPS [NXP Semiconductors]

网页	http://www.nxp.com

标志

2 / 12 page

April 1995

Philips Semiconductors

Product speciﬁcation

P-channel enhancement mode vertical

D-MOS transistor

BST120

DESCRIPTION

P-channel vertical D-MOS transistor

in SOT89 envelope and intended for

use in relay, high-speed and

line-transformer drivers, using SMD

technology.

FEATURES

• Very low R

DS(on)

• Direct interface to C-MOS

• High-speed switching

• No second breakdown

QUICK REFERENCE DATA

PINNING - SOT89

Drain-source voltage

−VDS

max.

60 V

Gate-source voltage (open drain)

±VGSO

max.

20 V

Drain current (DC)

−I

max.

0,3 A

Total power dissipation up to Tamb =25 °CPtot

max.

1 W

Drain-source ON-resistance

typ.

max.

4,5

Ω

−I

D = 200 mA; −VGS = 10 V

RDS(on)

Transfer admittance

−I

D = 200 mA; −VDS = 15 V

 Yfs

typ.

200 mS

1 = source

2 = drain

3 = gate

PIN CONFIGURATION

Fig.1 Simplified outline and symbol.

marking: LM

handbook, halfpage

MAM354

Bottom view

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