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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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WM8985GEFL/R 数据表(PDF) 21 Page - Wolfson Microelectronics plc |
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WM8985GEFL/R 数据表(HTML) 21 Page - Wolfson Microelectronics plc |
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21 / 118 page  Pre-Production WM8985 w PP, Rev 3.4, October 2006 21 INTERNAL POWER ON RESET CIRCUIT Figure 7 Internal Power on Reset Circuit Schematic The WM8985 includes an internal Power-On-Reset Circuit, as shown in Figure 7, which is used to reset the digital logic into a default state after power up. The POR circuit is powered from AVDD1 and monitors DCVDD. It asserts PORB low if AVDD1 or DCVDD is below a minimum threshold. Figure 8 Typical Power up Sequence where AVDD1 is Powered before DCVDD Figure 8 shows a typical power-up sequence where AVDD1 comes up first. When AVDD1 goes above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is asserted low and the chip is held in reset. In this condition, all writes to the control interface are ignored. Now AVDD1 is at full supply level. Next DCVDD rises to Vpord_on and PORB is released high and all registers are in their default state and writes to the control interface may take place. On power down, where AVDD1 falls first, PORB is asserted low whenever AVDD1 drops below the minimum threshold Vpora_off. |
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