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CS42L52 数据表(PDF) 21 Page - Cirrus Logic

部件名 CS42L52
功能描述  Low Power, Stereo CODEC w/Headphone & Speaker Amps
PDF  82 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS42L52 数据表(HTML) 21 Page - Cirrus Logic

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DS680A1
21
CS42L52
SWITCHING SPECIFICATIONS - SERIAL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL, SDOUT CLOAD = 15 pF.)
14. After powering up the CS42L52, RESET should be held low after the power supplies and clocks are
settled.
15. See “Example System Clock Frequencies” on page 77 for typical MCLK frequencies.
Parameters
Symbol
Min
Max
Units
RESET pin Low Pulse Width
(Note 14)
1-
ms
MCLK Frequency (Note 15)
(See “Serial Port Clock-
ing” on page 34)
MHz
MCLK Duty Cycle
45
55
%
Slave Mode
Input Sample Rate (LRCK)
Fs
(See “Serial Port Clock-
ing” on page 34)
kHz
LRCK Duty Cycle
45
55
%
SCLK Frequency
1/tP
-
64•Fs
Hz
SCLK Duty Cycle
45
55
%
LRCK Setup Time Before SCLK Rising Edge
ts(LK-SK)
40
-
ns
LRCK Edge to SDOUT MSB Output Delay
td(MSB)
-52
ns
SDOUT Setup Time Before SCLK Rising Edge
ts(SDO-SK)
20
-
ns
SDOUT Hold Time After SCLK Rising Edge
th(SK-SDO)
30
-
ns
SDIN Setup Time Before SCLK Rising Edge
ts(SD-SK)
20
-
ns
SDIN Hold Time After SCLK Rising Edge
th
20
-
ns
Master Mode
Output Sample Rate (LRCK)
All Speed Modes
Fs
(See “Serial Port Clock-
ing” on page 34)
Hz
LRCK Duty Cycle
45
55
%
SCLK Frequency
SCLK=MCLK mode
1/tP
-
12.0000
MHz
MCLK=12.0000 MHz
1/tP
-
68•Fs
Hz
all other modes
1/tP
-
64•Fs
Hz
SCLK Duty Cycle
45
55
%
LRCK Edge to SDOUT MSB Output Delay
td(MSB)
-52
ns
SDOUT Setup Time Before SCLK Rising Edge
ts(SDO-SK)
20
-
ns
SDOUT Hold Time After SCLK Rising Edge
th(SK-SDO)
30
-
ns
SDIN Setup Time Before SCLK Rising Edge
ts(SD-SK)
20
-
ns
SDIN Hold Time After SCLK Rising Edge
th
20
-
ns
th(SK-SDO)
//
//
//
//
//
//
//
//
ts(SD-SK)
MSB
MSB
MSB-1
MSB-1
LRCK
SCLK
SDOUT
SDIN
td(MSB)
ts(LK-SK)
tP
th
ts(SDO-SK)
Figure 3. Serial Audio Interface Timing



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