AS8579-ASST datasheet(28/44 Pages) AMSCO

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AS8579

Datasheet

• PUBLIC

DS000707

• v4-01 • 2022-Jun-08

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Figure 24:

I-Channel Data

Name

Bit String (13:0)

Read/Write

Description

ACCU I

XX00 0000 0000 0000

Data Register

7.2.4

Q-Channel Data (Address 0x04)

According to the register settings the Accumulated Data for the Q-Channel. Dependent on the

accumulation setting in the ADCTL register (0x2A/0x3A), the value can be from 12 up to 14 bits.

The content of the register can be read out with command 0x90.

Figure 25:

Q-Channel Data

Name

Bit String (13:0)

Read/Write

Description

ACCU Q

XX00 0000 0000 0000

Data Register

7.2.5

ADC Status Register (Address 0x05)

The 0x05 command is used to read the “ADC Complete” status bit (Bit [0] from Register 0x05). This bit

is set when the ADC has completed the accumulation of the programmed samples of both the I and Q

data signals and placed the data in the SPI output registers. The bit is cleared upon reading the

combined data registers (0x90 command) or when a new ADC cycle is initiated.

Figure 26:

ADC Status

Name

Bit Position

Read/Write

Measurement Data

ADC complete

Bit is set (1) when ADC has completed

accumulation.

7.2.6

CLK_E Timing Selection Register (Address 0x20/0x30)

The 0x30 command controls the division factor (EDIV [3:0]) applied to CLK_E pin to generate the

internal system clock. The division factor is programmable from 1 to 12. Default value at power-up is

12. The 0x20 command is used to read the current value of EDIV. The applied system clock must be

at 4 MHz after the CLK_E Frequency dividing factor. (e.g.48 MHz / 12 = 4 MHz)

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