DS691A3

21

CS4350

2.

Bring RST high. The device will remain in a low-power state with VQ low.

3.

Perform a control port write to a valid register prior to the completion of approximately 512 LRCK

cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in

Quad-Speed Mode). The desired register settings can be loaded while keeping the PDN bit set to 1.

4.

Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µs when

the Popguard is disabled. If the Popguard is enabled, see Section 4.7 for a complete description of

power-up timing.

4.7

The CS4350 uses a novel technique to minimize the effects of output transients during power-up and power-

down. This technology, when used with external DC-blocking capacitors in series with the audio outputs,

minimizes the audio transients commonly produced by single-ended single-supply converters. It is activated

inside the DAC when the RST pin is toggled and requires no other external control, aside from choosing the

appropriate DC-blocking capacitors.

4.7.1

Power-Up

When the device is initially powered-up, the audio outputs, AOUTA and AOUTB, are clamped to GND.

Following a delay of approximately 1000 sample periods, each output begins to ramp toward the quies-

This gradual voltage ramping allows time for the external DC-blocking capacitors to charge to the quies-

cent voltage, minimizing audible power-up transients.

4.7.2

Power-Down

To prevent audible transients at power-down, the device must first enter its power-down state. When this

occurs, audio output ceases and the internal output buffers are disconnected from AOUTA and AOUTB.

In their place, a soft-start current sink is substituted which allows the DC-blocking capacitors to slowly dis-

charge. Once this charge is dissipated, the power to the device may be turned off, and the system is ready

for the next power-on.

4.7.3

Discharge Time

To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge be-

fore turning on the power or exiting the power-down state. If full discharge does not occur, a transient will

occur when the audio outputs are initially clamped to GND. The time that the device must remain in the

power-down state is related to the value of the DC-blocking capacitance and the output load. For example,

with a 3.3 µF capacitor, the minimum power-down time will be approximately 0.4 seconds.