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CS4525 数据表(PDF) 21 Page - Cirrus Logic |
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CS4525 数据表(HTML) 21 Page - Cirrus Logic |
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21 / 91 page ![]() DS726A1 21 CS4525 SERIAL AUDIO INPUT PORT SWITCHING SPECIFICATIONS Inputs: Logic 0 = DGND; Logic 1 = VD Notes: 7. After powering up the CS4525, RST should be held low until the power supplies and clocks are stable. Parameters Symbol Min Nominal Max Units Supported Input Sample Rates FSI 28.5 39.5 39.5 86.4 32 44.1 48 96 35.2 52.8 52.8 105.6 kHz kHz kHz kHz LRCK Duty Cycle 45 - 55 % SCLK Frequency Single-Speed Mode Double-Speed Mode 1/tp -- - 128•FSI 64•FSI Hz Hz SCLK Duty Cycle 45 - 55 % LRCK Setup Time Before SCLK Rising Edge ts(LK-SK) 40 - - ns SDIN Setup Time Before SCLK Rising Edge ts(SD-SK) 25 - - ns SDIN Hold Time After SCLK Rising Edge th 10 - - ns RST pin Low Pulse Width (Note 7)1 - - ms // // // // // // t s(SD-SK) MSB MSB-1 LRCK SCLK SDIN t r t f t s(LK-SK) t P t h Figure 7. Serial Audio Input Port Timing |
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