CS48500 Data Sheet

32-bit Audio Decoder DSP Family

DS734A3

21

CONFIDENTIAL

5.14 Switching Characteristics — DSD Slave Input Port

Parameter

Symbol

Min

Typ

Max

Unit

MCLK Duty Cycle

-

40

-

60

%

DSD_SCLK Pulse Width Low

78

-

-

ns

DSD_SCLK Pulse Width High

78

-

-

ns

DSD_SCLK Frequency

(64x Oversampled)

(128x Oversampled)

-

-

1.024

2.048

-

-

3.2

6.4

MHz

MHz

DSD_A / _B valid to DSD_SCLK rising setup time

20

-

-

ns

DSD_SCLK rising to DSD_A or DSD_B hold time

20

-

-

ns

DSD clock to data transition (Phase Modulation mode)

-20

-

20

ns

Figure 8. Direct Stream Digital - Serial Audio Input Timing

dpm

t

DSD_A, DSD_B

DSD_SC LK

(64Fs)

DSD_SC LK

(128F s)

dpm

t

Figure 9. Direct Stream Digital - Serial Audio Input Timing for Phase Modulation Mode