Nexperia

74HC594; 74HCT594

8-bit shift register with output register

25 °C

-40 °C to +85 °C -40 °C to +125 °C

Symbol Parameter Conditions

Min Typ Max

Min

Max

Min

Max

Unit

DS to SHCP; see Fig. 8

20

4

-

25

-

30

-

ns

SHR to STCP; see Fig. 9

20

6

-

25

-

30

-

ns

tsu

set-up time

SHCP to STCP; see Fig. 7

20

7

-

25

-

30

-

ns

th

hold time

DS to SHCP; see Fig. 8

5

-3

-

6

-

7

-

ns

trec

recovery

time

SHR to SHCP and

STR to STCP;

see Fig. 10 and Fig. 11

10

-5

-

13

-

15

-

ns

SHCP or STCP;

see Fig. 6 and Fig. 7

30

92

-

24

-

20

-

MHz

fmax

maximum

frequency

VCC = 5.0 V; CL = 15 pF

-

100

-

-

-

-

-

MHz

CPD

power

dissipation

capacitance

VI = GND to VCC - 1.5 V;

VCC = 5 V; fi = 1 MHz

[2]

-

89

-

-

-

-

-

pF

[1] tpd is the same as tPHL and tPLH.

[2] CPD is used to determine the dynamic power dissipation (PD in μW):

PD = CPD × VCC 2 × fi × N + ∑(CL × VCC 2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

∑(CL × VCC 2 × fo) = sum of outputs.

11.1. Waveforms and test circuit

001aae341

SHCP input

Q7S output

VM

tPLH

tTLH

tTHL

tPHL

VM

tW

1/fmax

Measurement points are given in Table 10.

Fig. 6. The shift clock (SHCP) to output (Q7S) propagation delays, the shift clock pulse width, the maximum shift

clock frequency, and output transition times

74HC_HCT594

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Product data sheet

Rev. 7 — 20 October 2022

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