Nexperia

74AXP1T45

1-bit dual supply translating transceiver; 3-state

12.2. Bidirectional logic level-shifting application

Fig. 16 shows the 74AXP1T45 being used in a bidirectional logic level-shifting application. Since

the device does not have an output enable pin, the system designer should take precautions to

avoid bus contention between system-1 and system-2 when changing directions.

aaa-029970

74AXP1T45

PULL-UP/DOWN

DIR CTRL

VCC(A)

VCC1

1

6

VCC(B)

VCC1

I/O-1

GND

system-1

2

5 DIR

A 3

4 B

PULL-UP/DOWN

system-2

VCC2

VCC2

I/O-2

Fig. 16. Bidirectional logic level-shifting application

Table 18 gives a sequence that will illustrate data transmission from system-1 to system-2 and then

from system-2 to system-1.

Table 18. Description bidirectional logic level-shifting application

H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.

State DIR CTRL I/O-1

I/O-2

Description

1

H

output

input

system-1 data to system-2

2

H

Z

Z

system-2 is getting ready to send data to system-1.

I/O-1 and I/O-2 are disabled. The bus-line state

depends on bus hold.

3

L

Z

Z

DIR bit is set LOW. I/O-1 and I/O-2 still are disabled.

The bus-line state depends on bus hold.

4

L

input

output

system-2 data to system-1

12.3. Enable times

Calculate the enable times for the 74AXP1T45 using the following formulas:

• Direction A to B:

• tPZL (DIR to B) = tPHL (A to B) + tPHZ (DIR to A)

• tPZH (DIR to B) = tPLH (A to B) + tPLZ (DIR to A)

• Direction B to A:

• tPZL (DIR to A) = tPHL (B to A) + tPHZ (DIR to B)

• tPZH (DIR to A) = tPLH (B to A) + tPLZ (DIR to B)

In a bidirectional application, these enable times provide the maximum delay from the time

the DIR bit is switched until an output is expected. For example, if the 74AXP1T45 initially is

transmitting from A to B, then the DIR bit is switched, the B port of the device must be disabled

before presenting it with an input. After the B port has been disabled, an input signal applied to it

appears on the corresponding A port after the specified propagation delay.

74AXP1T45

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© Nexperia B.V. 2022. All rights reserved

Product data sheet

Rev. 2 — 3 February 2022

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