WS1A3940

4

Rev. 03, 2023-02-04

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The information in this document is subject to change without notice.

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Pinout Diagram (top view)

Source

(metalized

backside)

Index

marking

Peak

Main

16

17

18

19

20

15

14

13

12

11

10

9

8

7

6

1

2

3

4

5

Source

(metalized

backside)

Index

marking

Peak

Main

16

17

18

19

20

15

14

13

12

11

10

9

8

7

6

1

2

3

4

5

RFIN(PEAK)

RFIN(PEAK)

GND

RFIN(MAIN)

RFOUT(MAIN) + VDS(MAIN)

RFOUT(MAIN) + VDS(MAIN)

RFIN(MAIN)

GND

RFOUT(PEAK) + VDS(PEAK)

RFOUT(PEAK) + VDS(PEAK)

Bias Sequencing

Bias ON

1.

Ensure RF is turned off

2.

Apply pinch-off voltage of –5 V to the gate

3.

Apply nominal drain voltage

4.

Bias gate to desired quiescent drain current

5.

Apply RF

Bias OFF

1.

Turn RF off

2.

Apply pinch-off voltage to the gate

3.

Turn-off drain voltage

4.

Turn-off gate voltage