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PPC5567MVR112R2 数据表(PDF) 49 Page - Freescale Semiconductor, Inc |
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PPC5567MVR112R2 数据表(HTML) 49 Page - Freescale Semiconductor, Inc |
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49 / 56 page  Mechanicals MPC5567 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without Notice Freescale Semiconductor 49 4 Mechanicals 4.1 Pinouts 4.1.1 MPC5567 416 PBGA Pinout Figure 33 is a pinout for the MPC5567 416 PBGA package. While the MPC5567 and the MPC5553/MPC5554 are pin-compatible, the MPC5567 ball map is shown here to highlight the balls that are not connected to any signals and the balls used for Ethernet. Figure 33. MPC5567 416 Package Of special note is ball Y25, which changes from VRCVSS on all other MPC5500 devices (currently defined) to PLLCFG2 on the MPC5567. PLLCFG2 is required to support a 40-MHz clock option for the FlexRay. VSS 1 2 3 4 5 6 7 8 9 10 11 1213 1415 1617 1819 2021 22 2324 2526 AN35 VSTBY AN37 AN11 VDDA1 AN16 AN5 VRH AN23 AN27 AN28 VSSA0 AN15 MDO11 MDO8 VDD VDD33 VSS A VDD AN32 VSS AN36 AN39 AN19 AN20 AN4 AN22 AN26 AN31 VSSA0 AN14 MDO10 MDO7 MDO4 MDO0 VSS VDDE7 B VDD33 AN33 VDD VSS AN8 AN17 VSSA1 AN3 AN7 VRL AN25 AN30 VDDA0 AN13 MDO9 MDO6 MDO3 MDO1 VSS VDDE7 VDD C AN34 VDD VSS AN38 AN9 AN18 AN2 AN6 AN24 AN29 AN12 MDO5 MDO2 VSS VDDE7 TCK TDI D VDD VDDE7 TMS TDO TEST E MSEO0 JCOMP EVTI EVTO F MSEO1 MCKO G RDY H J VSS VSS VSS VSS VDDE7 VDDE7 VDDE7 VDDE7 K VSS VSS VSS VSS VSS VSS VSS VDDE7 L VSS VDDE2 VDDE2 VSS VSS VSS VSS VDDE7 SINB M BDIP VSS TEA VDDE2 VDDE2 VSS VSS VSS VSS VDDE7 SOUTB PCSB3 PCSB0 PCSB1 N CS3 VSS CS2 CS1 CS0 VDDE2 VDDE2 VSS VSS VSS VSS VSS PCSA3 PCSB4 SCKB PCSB2 P WE3 VSS WE2 WE1 WE0 VDDE2 VDDE2 VSS VSS VSS VSS VSS PCSB5 SOUTA SINA SCKA R VDDE2 VDDE2 NC RD_WR VDDE2 VDDE2 VSS VDDE2 VDDE2 VDDE2 VSS VSS PCSA1 PCSA0 PCSA2 VPP T VDDE2 NC TA VDD33 VSS VDDE2 VDDE2 VDDE2 VDDE2 VSS VSS PCSA4 TXDA PCSA5 VFLASH U TS CNTXC RXDA RSTOUT V RXDB CNRXC TXDB RESET W VDDE2 Y EXTAL AA VDDE2 VDD XTAL AB VDDE2 VSS VDD VDDE2 VDDE5 NC_1 VSS VDD VRC33 AC VSS VDD VDD33 CNTXA VDDE5 NC_2 VSS VDD VDD33 AD BR VSS VDD OE BG CNRXA VDDE5 CLKOUT VSS VDD AE VSS VDD VDDE2 VDDE2 NC CNTXB CNRXB VDDE5 VSS AF A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 1 2 3 4 5 6 7 8 9 10 11 1213 1415 1617 1819 2021 22 2324 2526 AN10 AN21 AN0 AN1 ETRIG 1 FEC_ TX_CLK FEC_ TX_ER GPIO 205 ETRIG 0 FEC_ TXD2 FEC_ TXD1 FEC_ TXD0 FEC_ TX_EN FEC_ TXD3 ETPUA 30 ETPUA 31 VDDEH 9 FEC_ COL FEC_ CRS VDDEH 8 VDDEH 1 ETPUA 28 ETPUA 29 VDDEH 1 ETPUA 24 ETPUA 27 ETPUA 26 ETPUA 23 ETPUA 22 ETPUA 25 ETPUA 21 ETPUA 20 ETPUA 19 ETPUA 18 ETPUA 17 ETPUA 16 ETPUA 15 ETPUA 14 ETPUA 13 ETPUA 12 ETPUA 11 ETPUA 10 ETPUA 9 ETPUA 8 ETPUA 7 ETPUA 6 ETPUA 5 ETPUA 4 ETPUA 3 ETPUA 2 ETPUA 1 ETPUA 0 TCRCLK A VDDEH 10 GPIO 204 FEC_ RX_ER GPIO 203 FEC_ RX_DV VDDE 12 FEC_ RXD3 FEC_ RX_CLK FEC_ MDC FEC_ RXD1 FEC_ RXD0 FEC_ RXD2 VDDE 12 FEC_ MDIO ADDR 16 ADDR 18 ADDR 17 ADDR 8 ADDR 20 ADDR 19 ADDR 10 ADDR 9 ADDR 22 ADDR 21 ADDR 11 ADDR 24 ADDR 23 ADDR 12 ADDR 13 ADDR 25 ADDR 14 ADDR 15 ADDR 26 ADDR 27 ADDR 31 ADDR 28 ADDR 30 ADDR 29 DATA 16 DATA 18 DATA 17 DATA 19 DATA 24 DATA 21 DATA 25 DATA 26 DATA 20 DATA 23 DATA 27 DATA 28 DATA 22 GPIO 207 GPIO 206 DATA 0 DATA 29 DATA 30 DATA 31 DATA 8 DATA 9 DATA 2 DATA 4 DATA 6 DATA 1 DATA 3 DATA 11 DATA 10 DATA 13 DATA 5 DATA 7 DATA 15 DATA 12 DATA 14 EMIOS 3 EMIOS 1 EMIOS 0 EMIOS 6 EMIOS 5 EMIOS 4 EMIOS 2 EMIOS 10 EMIOS 9 EMIOS 7 EMIOS 8 EMIOS 15 EMIOS 13 EMIOS 11 EMIOS 12 EMIOS 17 EMIOS 16 EMIOS 14 EMIOS 21 EMIOS 22 EMIOS 19 EMIOS 18 EMIOS 23 EMIOS 20 VDDEH 4 BOOT CFG1 VDDEH 6 PLL CFG1 BOOT CFG0 WKP CFG PLL CFG2 VSS SYN VRC CTL PLL CFG0 VDD SYN RST CFG ENG CLK Version 1.2 – 11 July 2005 REF BYPC NC NC NC NC NC VDDE 13 VDDE 13 NC NC NC NC NC NC No connect. AC22 & AD23 reserved NC_2 Note: No connect NC NC_1 |
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