Production Data

WM8152

w

PD Rev 4.0 January 2004

21

DEVICE CONFIGURATION

REGISTER MAP

The following table describes the location of each control bit used to determine the operation of the

WM8152. The register map is programmed by writing the required codes to the appropriate

addresses via the serial interface.

BIT

ADDRESS

<a5:a0>

DESCRIPTION

DEF

(hex)

RW

b7

b6

b5

b4

b3

b2

b1

b0

000001

Setup Reg 1

0F

RW

0

MODE3

PGAFS[1]

PGAFS[0]

1

1

CDS

EN

000010

Setup Reg 2

23

RW

DEL[1]

DEL[0]

RLCDACRNG

0

VRLCEXT

INVOP

1

1

000011

Setup Reg 3

1F

RW

0

0

CDSREF [1]

CDSREF [0]

RLCV[3]

RLCV[2]

RLCV[1]

RLCV[0]

000100

Software Reset

00

W

000110

Setup Reg 4

05

RW

0

0

INTM[1]

INTM[0]

RLCINT

1

0

1

000111

Revision Number

41

R

0

1

0

0

0

0

0

1

001000

Setup Reg 5

00

RW

0

0

0

POSNNEG

VDEL[2]

VDEL[1]

VDEL[0]

VSMPDET

001001

Test Reg 1

00

RW

TCLK

0

0

0

0

0

0

0

001010

Reserved

00

RW

0

0

0

0

0

0

0

0

001011

Reserved

00

RW

0

0

0

0

0

0

0

0

001100

Reserved

00

RW

0

0

0

0

0

0

0

0

100000

DAC Value (Red)

80

RW

DACR[7]

DACR[6]

DACR[5]

DACR[4]

DACR[3]

DACR[2]

DACR[1]

DACR[0]

100001

DAC Value

(Green)

80

RW

DACG[7]

DACG[6]

DACG[5]

DACG[4]

DACG[3]

DACG[2]

DACG[1]

DACG[0]

100010

DAC Value (Blue)

80

RW

DACB[7]

DACB[6]

DACB[5]

DACB[4]

DACB[3]

DACB[2]

DACB[1]

DACB[0]

100011

DAC Value (RGB)

80

W

DAC[7]

DAC[6]

DAC[5]

DAC[4]

DAC[3]

DAC[2]

DAC[1]

DAC[0]

101000

PGA Gain (Red)

00

RW

PGAR[7]

PGAR[6]

PGAR[5]

PGAR[4]

PGAR[3]

PGAR[2]

PGAR[1]

PGAR[0]

101001

PGA Gain

(Green)

00

RW

PGAG[7]

PGAG[6]

PGAG[5]

PGAG[4]

PGAG[3]

PGAG[2]

PGAG[1]

PGAG[0]

101010

PGA Gain (Blue)

00

RW

PGAB[7]

PGAB[6]

PGAB[5]

PGAB[4]

PGAB[3]

PGAB[2]

PGAB[1]

PGAB[0]

101011

PGA Gain (RGB)

00

W

PGA[7]

PGA[6]

PGA[5]

PGA[4]

PGA[3]

PGA[2]

PGA[1]

PGA[0]

Table 4 Register Map