IDT7134LA55CB datasheet(10/11 Pages) IDT

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IDT7134SA/LA

High-Speed 4K x 8 Dual-Port Static SRAM

Military, Industrial and Commercial Temperature Ranges

Truth Table I Read/Write Control

Functional Description

The IDT7134 provides two ports with separate control, address,

and I/O pins that permit independent access for reads or writes to any

location in memory. These devices have an automatic power down

featurecontrolledbyCE.TheCEcontrolson-chippowerdowncircuitry

that permits the respective port to go into standby mode when not

selected (CE HIGH). When a port is enabled, access to the entire

memory array is permitted. Each port has its own Output Enable

control(OE).Inthereadmode,theports OEturnsontheoutputdrivers

whensetLOW.Non-contentionREAD/WRITEconditionsareillustrated

in the table below.

Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,4)

NOTES:

1. R/W or CE must be HIGH during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of a CE =VIL and R/W = VIL.

3. tWR is measured from the earlier of CE or R/W going HIGH to the end-of-write cycle.

4. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

5. Timing depends on which enable signal (CE or R/W) is asserted last.

NOTE:

1. A0L - A11L ≠ A0R - A11R

"H" = VIH, "L" = VIL, "X" = Dont Care, and "Z" = High Impedance

Left or Right Port(1)

R/W

D0-7

Function

Port Deselected and in Power-Down

Mode, ISB2 or ISB4

CER

= CEL = H, Power Down

Mode ISB1 or ISB3

DATAIN

Data on port written into memory

DATAOUT Data in memory output on port

High impedance outputs

2720 tbl 11

2720 drw 12

tWC

ADDRESS

DATAIN

tDW

tWR

(3)

tDH

tEW

(2)

tAW

tAS

(5)

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