1–84
Product Data Sheets
ISD2500 Series
-1
specification. The frequency is then maintained to
a variation of
±2.25% over the entire commercial
temperature and operating voltage ranges. The
internal clock has a
±5% tolerance over the indus-
trial temperature and voltage range. A regulated
power supply is recommended for industrial tem-
perature range parts. If greater precision is
required, the device can be clocked through the
XCLK pin as follows:
These recommended clock rates should not be
varied because the antialiasing and smoothing fil-
ters are fixed, and aliasing problems can occur if
the sample rate differs from the one recom-
mended. The duty cycle on the input clock is not
critical, as the clock is immediately divided by two.
IF THE XCLK IS NOT USED
, THIS INPUT MUST BE CON-
NECTED TO GROUND
.
Speaker Outputs (SP+/SP-)
All devices in the ISD2500 Series include an on-
chip differential speaker driver, capable of driving
50 milliwatts into 16
Ω from AUX IN (12.2 mW from
memory).
The speaker outputs are held at VSSA levels during
record and power down. It is therefore not possible
to parallel speaker outputs of multiple ISD2500
devices or the outputs of other speaker drivers.
NOTE
Connection of speaker outputs in parallel
may cause damage to the device.
A single output may be used alone (including a
coupling capacitor between the SP pin and the
speaker). These outputs may be used individually
with the output signal taken from either pin. Using
the differential outputs results in a 4:1 improve-
ment in output power.
NOTE
Never ground or drive an unused speaker
output.
Auxiliary Input (AUX IN)
The Auxiliary Input is multiplexed through to the
output amplifier and speaker output pins when CE
is HIGH, P/R is HIGH, and Playback is currently
not active or if the device is in Playback overflow.
When cascading multiple ISD2500 devices, the
AUX IN pin is used to connect a Playback signal
from a following device to the previous output
speaker drivers. For noise considerations, it is sug-
gested that the auxiliary input not be driven when
the storage array is active.
Address/Mode Inputs (Ax/Mx)
The Address/Mode Inputs have two functions
depending on the level of the two Most Significant
Bits (MSB) of the address (A8 and A9 for the
ISD256075/90/120 devices, and A7 and A8 for the
ISD2532/40/48/64* devices).
If either or both of the two MSBs are LOW, the
inputs are ALL interpreted as address bits and are
used as the start address for the current Record or
Playback cycle. The address pins are inputs only
and do not output internal address information as
the operation progresses. Address inputs are
latched by the falling edge of CE.
If both MSBs are HIGH, the Address/Mode Inputs
are interpreted as Mode bits according to the
Operational Mode table on page 1-85. There are
six operational modes (M0..M6) available as indi-
Part
Number
Sample Rate
Required Clock
ISD2560
8.0 KHz
1024 KHz
ISD2575
6.4 KHz
819.2 KHz
ISD2590
5.3 KHz
682.7 KHz
ISD25120
4.0 KHz
512 KHz
ISD2532*
8.0 KHz
1024 KHz
ISD2540*
6.4 KHz
819.2 KHz
ISD2548*
5.3 KHz
682.7 KHz
ISD2564*
4.0 KHz
512 KHz
* Advance information: ISD2532/40/48/64 devices.
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