GWIXP420BBT datasheet(43/134 Pages) INTEL

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Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor

Datasheet

March 2005

Document Number: 252479, Revision: 005

UTP_IP_FCI

UTOPIA Input Data flow control input signal. Also known

as RXEMPTY/CLAV.

Used to inform the processor of the ability of each polled

PHY to send a complete cell. For cell-level flow control in

an MPHY environment, RxClav is an active high tri-

stateable signal from the MPHY to ATM layer. The

UTP_IP_FCI, which is connected to multiple MPHY

devices, will see logic high generated by the PHY, one

clock after the given PHY address is asserted, when a full

cell can be received by the PHY. The UTP_IP_FCI will see

a logic low generated by the PHY, one clock cycle after the

PHY address is asserted if a full cell cannot be received

by the PHY.

In SPHY mode, this signal is used to indicate to the

processor that the PHY has an octet or cell available to be

transferred to the

processor.

Should be pulled low through a 10-K

Ω resistor when not

being utilized in the system.

UTP_IP_SOC

Start of Cell. RX_SOC

Active-high signal that is asserted when UTP_IP_DATA

contains the first valid byte of a transmitted cell.

Should be pulled low through a 10-K

Ω resistor when not

being utilized in the system.

UTP_IP_DATA[7:0]

UTOPIA input data. Also known as RX_DATA.

Used by to the processor to receive data from an ATM

UTOPIA-Level-2-compliant PHY.

Should be pulled low through a 10-K

Ω resistor when not

being utilized in the system.

UTP_IP_ADDR[4:0]

Receive PHY address bus.

Used by the processor when operating in MPHY mode to

poll and select a single PHY at any one given time.

UTP_IP_FCO

UTOPIA Input Data Flow Control Output signal: Also

known as the RX_ENB_N.

In SPHY configurations, UTP_IP_FCO is used to inform

the PHY that the processor is ready to accept data.

In MPHY configurations, UTP_IP_FCO is used to select

which PHY will drive the UTP_RX_DATA and

UTP_RX_SOC signals. The PHY is selected by placing

the PHY’s address on the UTP_IP_ADDR and bringing

UTP_OP_FCO to logic 1 during the current clock, followed

by the UTP_OP_FCO going to a logic 0 on the next clock

cycle.

Table 11.

UTOPIA-2 Interface (Sheet 2 of 2)

Name

Power

Reset1

Reset2

Type†

Description

While PWRON_RESET_N is deasserted use Power On Reset column for the pin state.

After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of

PLL_LOCK, all signals reflect the value shown in the RESET column.

†

For a legend of the Type codes, see Table 5 on page 33.

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