GWIXC1100BBT datasheet(42/134 Pages) INTEL

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Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor

March 2005

Datasheet

Document Number: 252479, Revision: 005

Table 11.

UTOPIA-2 Interface (Sheet 1 of 2)

Name

Power

Reset1

Reset2

Type†

Description

UTP_OP_CLK

UTOPIA Transmit clock input. Also known as

UTP_TX_CLK. This signal is used to synchronize all

UTOPIA-transmit outputs to the rising edge of the

UTP_OP_CLK.

This signal should be pulled low through a 10-K

Ω resistor

when not being utilized in the system.

UTP_OP_FCO

UTOPIA flow control output signal. Also known as the

TXENB_N signal.

Used to inform the selected PHY that data is being

transmitted to the PHY. Placing the PHY’s address on the

UTP_OP_ADDR — and bringing UTP_OP_FCO to logic

1, during the current clock — followed by the

UTP_OP_FCO going to a logic 0, on the next clock cycle,

selects which PHY is active in MPHY mode.

In SPHY configurations, UTP_OP_FCO is used to inform

the PHY that the processor is ready to send data.

UTP_OP_SOC

Start of Cell. Also known as TX_SOC.

Active high signal is asserted when UTP_OP_DATA

contains the first valid byte of a transmitted cell.

UTP_OP_DATA[7:0]

UTOPIA output data. Also known as UTP_TX_DATA.

Used to send data from the

processor to an ATM UTOPIA-

Level-2-compliant PHY.

UTP_OP_ADDR[4:0]

Transmit PHY address bus. Used by the

processor when

operating in MPHY mode to poll and select a single PHY

at any given time.

UTP_OP_FCI

UTOPIA Output data flow control input: Also known as the

TXFULL/CLAV signal.

Used to inform the processor of the ability of each polled

PHY to receive a complete cell. For cell-level flow control

in an MPHY environment, TxClav is an active high tri-

stateable signal from the MPHY to ATM layer. The

UTP_OP_FCI, which is connected to multiple MPHY

devices, will see logic high generated by the PHY, one

clock after the given PHY address is asserted — when a

full cell can be received by the PHY. The UTP_OP_FCI

will see a logic low generated by the PHY one clock cycle,

after the PHY address is asserted — if a full cell cannot be

received by the PHY.

This signal should be tied low through a 10-K

Ω resistor if

not being used.

UTP_IP_CLK

UTOPIA Receive clock input. Also known as

UTP_RX_CLK.

This signal is used to synchronize all UTOPIA-received

inputs to the rising edge of the UTP_IP_CLK.

This signal should be pulled low through a 10-K

Ω resistor

when not being utilized in the system.

While PWRON_RESET_N is deasserted use Power On Reset column for the pin state.

After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of

PLL_LOCK, all signals reflect the value shown in the RESET column.

†

For a legend of the Type codes, see Table 5 on page 33.

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