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74LV393D 数据表(PDF) 8 Page - Nexperia B.V. All rights reserved |
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74LV393D 数据表(HTML) 8 Page - Nexperia B.V. All rights reserved |
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8 / 13 page ![]() Nexperia 74LV393 Dual 4-bit binary ripple counter 001aad538 output nQx VOL VOH GND VI GND VI VM tPHL VM input nMR VM tW trec input nCP Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 9. Propagation delays clock (nCP) to output (nQx), pulse width master reset (nMR), and recovery time master reset (nMR) to clock (nCP) VM VM tW tW 10 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % tf tr tr tf 001aae331 VEXT VCC VI VO DUT CL RT RL RL G Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig. 10. Test circuit for measuring switching times Table 9. Test data Supply voltage Input Load VEXT VCC VI tr, tf CL RL tPHL, tPLH < 2.7 V VCC ≤ 2.5 ns 50 pF 1 kΩ open 2.7 V to 3.6 V 2.7 V ≤ 2.5 ns 15 pF, 50 pF 1 kΩ open 74LV393 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 6 — 19 March 2021 8 / 13 |
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