RT9603

Preliminary

2

DS9603-00

November 2003

www.richtek.com

Typical Application Circuit

Note: The traces that run from the controller ISPx and ISNx pins, should be run together next to each other and Kelvin connected

to the Q2. Place both R2 and R3 as close to the PWM Controller as possible.

Functional Pin Description

Pin No.

Pin Name

Pin Function

1

BST

Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor

between this pin and the SW pin. The bootstrap capacitor provides the charge to turn

on the upper MOSFET.

2

IN

Accepts a logic control signal. Connect this pin to the PWM output of the controller.

If the PWM signal enters and remains within the shutdown window, the output drivers are

disabled and both MOSFET gates are pulled and held low.

3

NC

No Internal Connection.

4

VCC

Supply Input. Connect to +12V supply. Place a bypass capacitor from this pin to PGND.

5

DRVL

Lower gate drive output. Should be connected to the lower MOSFET gate.

6

PGND

Common Ground.

7

SW

Upper driver return. Should be connected to the common node of upper and lower

MOSFETs. The SW voltage is monitored for adaptive shoot-through protection.

8

DRVH

Upper gate drive output. Should be connected to the upper MOSFET gate.

VCC

NC

IN

PGND

BST

DRVH

SW

DRVL

4

1

8

7

5

6

2

3

C1

1uF

+12V

10

PHB95N03LT

C2

1uF

C3

1uF

C4

1000uF/16V

PHB83N03LT

L1

2uH

C5

x1500uF

C6

x1500uF

VCORE

+12V

R2

2.4K

R3

2.4K

ISPx

ISNx

PWM

INPUT

Q2

Q1

R1

1N4148

D1