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CLC031AVEC 数据表(PDF) 7 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 CLC031AVEC
功能描述  SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancillary Data FIFOs
PDF  31 Pages
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

CLC031AVEC 数据表(HTML) 7 Page - National Semiconductor (TI)

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AC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3).
Symbol
Parameter
Conditions
Reference
Min
Typ
Max
Units
Serial Video Data Inputs
BR
SDI
Serial Input Data Rate
SMPTE 259M, Level C
SDI, SDI
270
M
BPS
SMPTE 259M, Level D
360
SMPTE 344M
540
SMPTE 292M
1,483
SMPTE 292M
1,485
t
r,tf
Rise Time, Fall Time
20%–80%, SMPTE 259M
Data Rates
0.4
1.0
1.5
pns
20%–80%, SMPTE 292M
Data Rates
270
ps
Parallel Video Data Outputs
f
VCLK
Video Output Clock
Frequency
SMPTE 259M, 270M
BPS
V
CLK
27.0
MHz
SMPTE 267M, 360M
BPS
36.0
SMPTE 344M, 540M
BPS
54.0
SMPTE 292M, 1,483M
BPS
74.176
SMPTE 292M, 1,485M
BPS
74.25
t
pd
Propagation Delay, Video
Clock to Video Data Valid
50%–50%
V
CLK to DVN
Timing Diagram
0.5
2.0
ns
DC
V
Duty Cycle, Video Clock
V
CLK
50±5%
t
JIT
Video Data Output Clock
Jitter
27MHz
V
CLK
2.0
ns
P-P
36MHz
1.4
54MHz
1.0
74.25MHz
0.5
Parallel Ancillary / Control Data Inputs, Multi-function Parallel Bus Inputs
f
ACLK
Ancillary / Control Data
Clock Frequency
A
CLK
V
CLK
MHz
DC
A
Duty Cycle, Ancillary Data
Clock
ANC Data clock
(Note 7)
45
50
55
%
t
r,tf
Output Rise Time, Fall
Time
10%–90%
IO
N,ADN,ACLK
Timing Diagram
1.0
1.5
3.0
ns
t
S
Setup Time, AD
N to ACLK
or IO
N to ACLK Rising Edge
Control Data Input or I/O
Bus Input
3.0
1.5
t
H
Hold Time, Rising Edge
A
CLK to ADN or ACLK to
IO
N
3.0
1.5
Parallel Ancillary / Control Data Outputs
t
pd
Propagation Delay, Clock
to Control Data
50%–50%
A
CLK to ADN
Timing Diagram
8.5
ns
t
pd
Propagation Delay, Clock
to Ancillary Data
11.5
Multi-function Parallel I/O Bus
t
r,tf
Rise Time, Fall Time
10%–90%
IO0–IO7
Timing Diagram
1.0
1.5
3.0
ns
PLL/CDR, Format Detect
t
LOCK
Lock Detect Time
SD Rates (Note 5)
0.32
1.0
ms
HD Rates (Note 5)
0.26
1.0
t
FORMAT
Format Detect Time
All Rates
20
Note 1: “Absolute Maximum Ratings” are those parameter values beyond which the life and operation of the device cannot be guaranteed. The stating herein of
these maximums shall not be construed to imply that the device can or should be operated at or beyond these values. The table of “Electrical Characteristics”
specifies acceptable device operating conditions.
www.national.com
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