S5935QF datasheet(21/190 Pages) AMCC

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SIGNAL DESCRIPTIONS

S5935

NON-VOLATILE MEMORY INTERFACE SIGNALS

This signal grouping provides for connection to external non-volatile memories. Either a serial or byte-wide device

may be used.

The serial interface shares the read and write control pins used for interfacing with byte-wide memory devices. Since

it is intended that only one (serial or byte wide) configuration be used in any given implementation, separate

descriptions are provided for each. The S5935 provides the pins necessary to interface to a byte wide non-volatile

memory. When they are connected to a properly configured serial memory, these byte wide interface pins assume

alternate functions. These alternate functions include added external FIFO status flags, FIFO reset control, Add-On

control for bus mastering and a hardware interface mailbox port.

Byte-Wide nv Devices

Signal

Type

Description

SCL

t/s

Serial Clock. This output is intended to drive a two-wire Serial Interface and functions

as the bus’s master. It is intended that this signal be directly connected to one or

more inexpensive serial non-volatile RAMs or EEPROMs. This pin is shared with the

byte wide interface signal, ERD#.

SDA

t/s

Serial Data/Address. This bidirectional pin is used to transfer addresses and data to or from

a serial nvRAM or EEPROM. It is an open drain output and intended to be wire-ORed

with all other devices on the serial bus using a 4.7K external pull-up resistor. This pin

is shared with the byte wide interface signal, EWR#.

SNV

Serial Non-Volatile Device. This input, when high, indicates a serial boot device or no

boot device is present. When this pin is low, a byte-wide boot device is present.

Serial nv Devices

Signal

Type

Description

EA[15:00]

t/s

External nv memory address. These signals connect directly to the external BIOS (or

EEPROM) or EPROM address pins EA0 through EA15. The PCI interface controller

assembles 32-bit-wide accesses through multiple read cycles of the 8-bit device. The

address space from 0040h through 007Fh is used to preload and initialize the PCI

configuration registers. Should an external nv memory be used, the minimum size

required is 128 bytes and the maximum is 64K bytes. When a serial memory is

connected to the S5935, the pins EA[7:0] are reconfigured to become a hardware Add-

On to PCI mailbox register with the EA8 pin as the mailbox load clock. Also, the EA15

signal pin will provide an indication that the PCI to Add-On FIFO is full (FRF#), and the

EA14 signal pin will indicate whether the Add-On to PCI FIFO is empty (FWE#).

ERD#

out

External nv memory read control. This pin is asserted during read operations involv-

ing the external non-volatile memory. Data is transferred into the S5935 during the

low to high transition of ERD#. This pin is shared with the serial external memory

interface signal, SCL.

EWR#

t/s

External nv memory write control. This pin is asserted during write operations involv-

ing the external non-volatile memory. Data is presented on pins EQ[7:0] along with its

address on pins EA[15:0] throughout the entire assertion of EWR#. This pin is shared

with the serial external memory interface signal, SDA.

EQ[7:0]

t/s

External memory data bus. These pins are used to directly connect with the data pins

of an external non-volatile memory. When a serial memory is connected to the

S5935, the pins EQ4, EQ5, EQ6 and EQ7 become reconfigured to provide signal

pins for bus mastering control from the Add-On interface.

Note: SCL and SDA are not controlled by FLT#.

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