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TIMING REQUIREMENTS

(1)

CDCDLP223

SCAS836 – DECEMBER 2006

over recommended ranges of supply voltage, load and operating free air temperature

PARAMETER

MIN

TYP

MAX

UNIT

XIN, XOUT REQUIREMENTS

20

MHz

capacitance

2 WIRE SERIAL INTERFACE REQUIREMENTS STANDARD MODE

SCLK frequency

0

100

kHz

START hold time (see Figure 1)

4.0

µs

SCLK low-pulse duration (see Figure 1)

4.7

µs

SCLK high-pulse duration (see Figure 1)

4.0

µs

START setup time (see Figure 1)

4.7

µs

SDATA hold time (see Figure 1)

0

3.45

µs

SDATA setup time (see Figure 1)

250

ns

SCLK / SDATA input rise time (see Figure 1)

1000

ns

SCLK / SDATA input fall time (see Figure 1)

300

ns

STOP setup time (see Figure 1)

4.0

µs

Bus free time

4.7

µs

2 WIRE SERIAL INTERFACE REQUIREMENTS FAST MODE

SCLK frequency

0

400

kHz

START hold time (see Figure 1)

0.6

µs

SCLK low-pulse duration (see Figure 1)

1.3

µs

SCLK high-pulse duration (see Figure 1)

0.6

µs

START setup time (see Figure 1)

0.6

µs

SDATA hold time (see Figure 1)

0

0.9

µs

SDATA setup time (see Figure 1)

100

ns

SCLK / SDATA input rise time (see Figure 1)

20

300

ns

SCLK / SDATA input fall time (see Figure 1)

20

300

ns

STOP setup time (see Figure 1)

0.6

µs

Bus free time

1.3

µs

(1)

4

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