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17510 数据表(PDF) 8 Page - Freescale Semiconductor, Inc |
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17510 数据表(HTML) 8 Page - Freescale Semiconductor, Inc |
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8 / 14 page ![]() Analog Integrated Circuit Device Data 8 Freescale Semiconductor 17510 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 17510 is a monolithic H-Bridge power IC applicable to small DC motors used in portable electronics. The 17510 can operate efficiently with supply voltages as low as 2.0 V to as high as 15 V, and it can provide continuos motor drive currents of 1.2 A while handling peak currents up to 3.8 A. It is easily interfaced to low-cost MCUs via parallel 5.0 V- compatible logic. The device can be pulse width modulated (PWM-ed) at up to 200 kHz. The 17510 has four operating modes: Forward, Reverse, Brake, and Tri-Stated (High Impedance). Basic protection and operational features (direction, dynamic braking, PWM control of speed and torque, main power supply undervoltage detection and shutdown, logic power supply undervoltage detection and shutdown), in addition to the 1.0 A rms output current capability, make the 17510 a very attractive, cost-effective solution for controlling a broad range of small DC motors. In addition, a pair of 17510 devices can be used to control bipolar stepper motors. The 17510 can also be used to excite transformer primary windings with a switched square wave to produce secondary winding AC currents. As shown in Figure 2, 17510 Simplified Internal Block Diagram, page 2, the 17510 is a monolithic H-Bridge with built-in charge pump circuitry. For a DC motor to run, the input conditions need to be set as follows: ENable input logic HIGH, one INput logic LOW, and the other INput logic HIGH (to define output polarity). The 17510 can execute dynamic braking by setting both IN1 and IN2 logic HIGH, causing both low-side MOSFETs in the output H-Bridge to turn ON. Dynamic braking can also implemented by taking the ENable logic LOW. The output of the H-Bridge can be set to an open- circuit high-impedance (Z) condition by taking both IN1 and IN2 logic LOW. (refer to Table 5, Truth Table, page 7). The 17510 outputs are capable of providing a continuous DC load current of up to 1.2 A. An internal charge pump supports PWM frequencies to 200 kHz. The EN pin also controls the charge pump, turning it off when EN = LOW, thus allowing the 17510 to be placed in a power-conserving sleep mode. FUNCTIONAL PIN DESCRIPTION OUTPUT 1 AND OUTPUT2 (OUT1, OUT2) The OUT1 and OUT2 pins provide the connection to the internal power MOSFET H-Bridge of the IC. A typical load connected between these pins would be a small DC motor. These outputs will connect to either VM or PGND, depending on the states of the control inputs (refer to Table 5, Truth Table, page 7). POWER GROUND AND LOGIC GROUND (PGND, LGND) The power and logic ground pins (PGND and LGND) should be connected together with a very low-impedance connection. CHARGE PUMP RESERVOIR CAPACITOR (CRES) The CRES pin provides the connection for the external reservoir capacitor (output of the charge pump). Alternatively this pin can also be used as an input to supply gate-drive voltage from an external source via a series current-limiting resistor. The voltage at the CRES pin will be approximately three times the VDD voltage, as the internal charge pump utilizes a voltage tripler circuit. The V CRES voltage is used by the IC to supply gate drive for the internal power MOSFET H-Bridge. MOTOR SUPPLY VOLTAGE INPUT (VM) The VM pins carry the main supply voltage and current into the power sections of the IC. This supply then becomes controlled and/or modulated by the IC as it delivers the power to the load attached between OUT1 and OUT2. All VM pins must be connected together on the printed circuit board with as short as possible traces offering as low impedance as possible between pins. VM has an undervoltage threshold. If the supply voltage drops below the undervoltage threshold, the output power stage switches to a tri-state condition. When the supply voltage returns to a level that is above the threshold, the power stage automatically resumes normal operation according to the established condition of the input pins. CONTROL SIGNAL INPUT AND ENABLE CONTROL SIGNAL INPUT (IN1, IN2, EN) The IN1, IN2, and EN pins are input control pins used to control the outputs. These pins are 5.0 V CMOS-compatible inputs with hysteresis. The IN1, IN2, and EN work together to control OUT1 and OUT2 (refer to Table 5, Truth Table). GATE DRIVER INPUT (GIN) The GIN input controls the GOUT pin. When GIN is set logic LOW, GOUT supplies a level-shifted high-side gate drive signal to an external MOSFET. When GIN is set logic HIGH, GOUT is set to GND potential. |
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