LXT6155LE datasheet(23/50 Pages) INTEL

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Datasheet

155 Mbps SDH/SONET/ATM Transceiver — LXT6155

Figure 8. Software Mode

Figure 9. Serial Data Output Word Structure (Read Cycle: R/W=High)

Figure 10. Serial Data Input Word Structure (Write Cycle: R/W =Low)

2.6

Serial System Interface

The serial interface permits the LXT6155 to communicate with an Overhead Termination device at

155.52 Mbps. Data and clock lines are differential 3.3V LVPECL signals. Refer to Figure 11.

2.7

Parallel System Interface

Parallel interface allows the LXT6155 to communicate with the system chip at 19.44 MHz, 8 bits

per clock cycle. Data and clock lines are TTL compatible signals. Refer to Figure 12.

LXT6155

HWSEL

SDI

SCLK

VCC

Chip select in

Serial data in

Serial clock in

SDO

Serial data out

ADDR0, ADDR1

Device address settings

DON'T

CARE

Don't Care

SCLK

SDI

SDO

High Impedance

Don't Care

DON'T

CARE

R/W

Don't Care

SCLK

SDI

SDO

High Impedance

Don't Care

R/W

LXT6155LE 数据表(PDF) 23 Page - Intel Corporation

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