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PCF85116-3T/01 数据表(PDF) 13 Page - NXP Semiconductors |
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PCF85116-3T/01 数据表(HTML) 13 Page - NXP Semiconductors |
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13 / 21 page ![]() Philips Semiconductors PCF85116-3 2048 × 8-bit CMOS EEPROM with I2C-bus interface Product data Rev. 04 — 25 October 2004 13 of 21 9397 750 14217 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 12. Write cycle limits Table 9: Write cycle limits The power-on-reset circuit resets the I2C-bus logic with a set-up time of ≤10 µs. Enabling the chip is achieved by connecting the WP input to VSS. Symbol Parameter Conditions Min Typ Max Unit E/W cycle timing tE/W E/W cycle time - - 10 ms Endurance NE/W E/W cycle per byte Tamb = −40 to +85 °C 100000 - - cycles Tamb =22 °C 1000000 - - cycles |
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