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UPD17P218 数据表(PDF) 21 Page - Renesas Technology Corp |
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UPD17P218 数据表(HTML) 21 Page - Renesas Technology Corp |
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21 / 32 page ![]() µPD17P218 19 AC CHARACTERISTICS (Ta = –40 to +85 °C) Item Symbol Conditions MIN. TYP. MAX. Unit tCY1 VDD = 3.5 to 5.5 V 1.99 32.2 µs CPU Clock Cycle Time Note (Instruction Execution Time) tCY2 VDD = 2.2 to 5.5 V 3.98 32.2 µs tCY3 VDD = 2.0 to 5.5 V 7.96 32.2 µs tIOH1 VDD = 4.5 to 5.5 V 10.0 µs INT High-Level Width tIOH2 VDD = 2.0 to 5.5 V 50.0 µs tIOL1 VDD = 4.5 to 5.5 V 10.0 µs INT Low-Level Width tIOL2 VDD = 2.0 to 5.5 V 50.0 µs tRSL1 VDD = 4.5 to 5.5 V 10.0 µs RESET Low-Level Width tRSL2 VDD = 2.0 to 5.5 V 50.0 µs Note: CPU clock cycle time (instruction execution time) is determined depending on the connected oscillation frequency and SYSCK (RF: address 02H) in the register file. The following figure shows CPU clock cycle time tCY characteristics versus supply voltage VDD. 5 01 2 3 4 5 6 Supply voltage VDD [V] 2 3 4 5 6 7 8 9 10 32 40 2.2 V tCY vs VDD |
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