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数据搜索系统，热门电子元器件搜索 |
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UPD17P236 数据表(PDF) 8 Page - Renesas Technology Corp |
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UPD17P236 数据表(HTML) 8 Page - Renesas Technology Corp |
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8 / 34 page  µPD17P236 6 Data Sheet U14776EJ1V0DS00 BLOCK DIAGRAM P0A0 P0A1 P0A2 P0A3 P0A P0B0 (MD0) P0B1 (MD1) P0B2 (MD2) P0B3 (MD3) P0B P0C0 (D4) P0C1 (D5) P0C2 (D6) P0C3 (D7) P0C P0D0 (D0) P0D1 (D1) P0D2 (D2) P0D3 (D3) P0D P0E0 P0E1 P0E2 P0E3 P0E P1A0Note P1A RF SYSTEM REG. ALU OSC CPU Clock REM INT (VPP) VDD GND XIN (CLK) XOUT Instruction Decoder Power Supply Circuit Remote Control Divider 8-bit timer Interrupt Controller RESET Reset Controller Program Counter Stack (5 levels) RAM 223 × 4 bits One Time PROM 16,384 × 16 bits Basic Interval/ Watchdog Timer Note Input port or output port is selected depending on the product (see 2. PIN FUNCTIONS). Remark ( ): During PROM programming mode |
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