Nexperia

74ALVC32

Quad 2-input OR gate

12. Abbreviations

Table 10. Abbreviations

Acronym

Description

DUT

Device Under Test

ESD

ElectroStatic Discharge

HBM

Human Body Model

MM

Machine Model

TTL

Transistor-Transistor Logic

13. Revision history

Table 11. Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

74ALVC32 v.5

20210340

Product data sheet

-

74ALVC32 v.4

Modifications:

• Section 2: Reference to JESD36 removed.

• Table 4: Derating values for Ptot total power dissipation updated (errata).

74ALVC32 v.4

20200928

Product data sheet

-

74ALVC32 v.3

Modifications:

• The format of this data sheet has been redesigned to comply with the identity guidelines of

Nexperia.

• Legal texts have been adapted to the new company name where appropriate.

• Section 2 updated.

• Table 4: Derating values for Ptot total power dissipation have been updated.

• Package outline drawing of SOT762-1 (Fig. 10) updated.

74ALVC32 v.3

20140120

Product data sheet

-

74ALVC32 v.2

• The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

74ALVC32 v.2

20071210

Product data sheet

-

74ALVC32 v.1

74ALVC32 v.1

20021115

Product specification -

-

74ALVC32

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 5 — 30 April 2021

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