Nexperia

74ALVC574

Octal D-type flip-flop; positive edge-trigger; 3-state

5.2. Pin description

Table 2. Pin description

Symbol

Pin

Description

D0, D1, D2, D3, D4, D5, D6, D7

2, 3, 4, 5, 6, 7, 8, 9

data input

CP

11

clock input (LOW to HIGH, edge-triggered)

OE

1

output enable input (active LOW)

Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7

19, 18, 17, 16, 15, 14, 13, 12

3-state flip-flop output

VCC

20

supply voltage

GND

10

ground (0 V)

6. Functional description

Table 3. Function table

H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW to HIGH CP transition;

L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW to HIGH CP transition;

Z = high-impedance OFF-state; ↑ = LOW to HIGH clock transition.

Input

Output

Operating mode

OE

CP

Dn

Internal flip-flop

Qn

L

↑

l

L

L

Load and read register

L

↑

h

H

H

H

↑

l

L

Z

Load register and disable

outputs

H

↑

h

H

Z

7. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

Conditions

Min

Max

Unit

VCC

supply voltage

-0.5

+4.6

V

IIK

input clamping current

VI < 0 V

-50

-

mA

VI

input voltage

[1]

-0.5

+4.6

V

IOK

output clamping current

VO > VCC or VO < 0 V

-

±50

mA

output HIGH or LOW state

[1]

-0.5

VCC + 0.5 V

output 3-state

-0.5

+4.6

V

VO

output voltage

power-down mode; VCC = 0 V

-0.5

+4.6

V

IO

output current

VO = 0 V to VCC

-

±50

mA

ICC

supply current

-

100

mA

IGND

ground current

-100

-

mA

Tstg

storage temperature

-65

+150

°C

Ptot

total power dissipation

Tamb = -40 °C to +85 °C

-

500

mW

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

74ALVC574

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 3 — 30 April 2021

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