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CS5016 数据表(PDF) 32 Page - Cirrus Logic |
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CS5016 数据表(HTML) 32 Page - Cirrus Logic |
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32 / 46 page ![]() Calibration resolution Calibration time reset: interleave: burst: End of calibration indicator Throughput rate in loopback mode Input capacitance in fine-charge mode CS5012 18 bits. Results in DNL calibration to 1/64 LSB at 12 bits. 1,441,020 CLKIN cycles 72,051 conversions not functional EOC falls at the completion of a RESET calibration cycle in microprocessor mode only. In microprocessor-independent mode cycles after completion of a RESET calibration. The device acquires and converts in 64 CLKIN cycles for CLKIN=4MHz, but will require 68 CLKIN cycles at 100kHz through- put. This is due to excess delay on 275pF typical, unipolar mode CS5012A 15 bits. Results in DNL calibration to 1/8 LSB at 12 bits. 58,280 CLKIN cycles 2,014 conversions fully functional EOC falls in either microprocessor or microprocessor-independent mode at the completion of a RESET calibration cycle. The device acquires and converts a sample in 64 CLKIN cycles for all CLKIN frequencies when in loopback. 103pF typical, unipolar mode EOT must be used. EOT. Slew Rate Unipolar Coarse charge Fine charge Bipolar Coarse charge Fine charge falls 15 CLKIN EOT 20V/us 1.5V/us 40V/us 3.0V/us 5V/us 0.25V/us 10V/us 0.5V/us 72pF typical, bipolar mode 165pF typical, bipolar mode Table 3. Differences Between the CS5012A and CS5012 CS5012A, CS5014, CS5016 2-38 DS14F6 |
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