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UPD61P24CS 数据表(PDF) 14 Page - Renesas Technology Corp

部件名 UPD61P24CS
功能描述  MOS INTEGRATED CIRCUIT
PDF  38 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

UPD61P24CS 数据表(HTML) 14 Page - Renesas Technology Corp

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µPD61P24
12
12. PORT REGISTER (P×)
KI/O, KI, and the control register are handled as port registers.
The table below shows the relations between the port registers and pins.
Table 12-1. Relations between Port Registers and Pins
Pin
Input Mode
Output Mode
Name
Read
Write
Read
Write
On Reset
KI/O
Pin status
Output latch
Pin status
Output latch
Undefined [input mode, output latch]
KI
Pin status
–
–
–
Input mode
S-IN
Pin status is read by RL A instruction when D0 of P1 register = 1.
High impedance (D0 of P1 register = 0)
P 10
P 11
P 12
P 00
P 01
P 02
K I/O7-4
K I/O3-0
P 0
P 1
P 2
Control register (H)
Control register (L)
K I3-0
P1
× (H)
P0
× (L)



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