STV-DCASLASHCIF-R01 datasheet(22/105 Pages) STMICROELECTRONICS

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VV5410 & VV6410

Exposure Control

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note: The relationship between the programmed gain value as written to register[36] and the igain (current gain) and

cgain (capacitive gain) is as follows:

igain

If mode_select[24], bit 1 is set then igain[3:0] is the inverse of gain[3:0], i.e. if gain[3:0] = 6, igain[3:0] = 9.

If mode_select[24], bit 1 is reset then igain[3:0] is the inverse of the mirror of gain[3:0], i.e. bit 3 of igain is the inverse of bit 0 of

gain, i.e. gain = 4 and igain = 13.

cgain

cgain is a 6 bit value therefore we have to pad the 4 bits of the gain register. In 10bit modes cgain[1:0] is fixed at 2’b11 and

cgain[5:2] is set to gain[7:4]. In the 9bit modes cgain[1:0] is also set to 2’b11, however cgain[5:2] is set to gain[7:4] divided by 2,

thus gain[7:4] = 4’b1111 gives cgain[5:0] = 6’b011111.

6.2.1

Recommended Gain Settings

To ensure optimum sensor performance it is recommended that the igain setting, controlled by the ls nibble of serial

6.3

Clock Division

Although the clock divisor register is an 8 bit register the user only has write access to the lower 4 bits as described above. The

upper 4 bits of the register are altered automatically when the video mode is changed by writing to Setup0[16] register. The upper

4 bits are pre-programmed as follows:

10bit ADC mode

9bit ADC mode

gain[7:0]

igain[3:0]

cgain[5:0]

Overall

Gain

gain[7:0]

igain[3:0]

cgain[5:0]

Overall

Gain

8’hfe

1 (00012)

8.000

8’hfe

1 (00012)

8.000

8’hfd

2 (00102)

5.333

8’hfd

2 (00102)

5.333

8’fc

3 (00112)

4.000

8’fc

3 (00112)

4.000

8’hfb

4 (01002)

3.200

8’hfb

4 (01002)

3.200

8’hfa

5 (01012)

2.667

8’hfa

5 (01012)

2.667

8’hf9

6 (01102)

2.2857

8’hf9

6 (01102)

2.2857

8’hf8

7 (01112)

2.0000

8’hf8

7 (01112)

2.0000

8’hf7

8 (10002)

1.7778

8’hf7

8 (10002)

1.7778

8’hf6

9 (10012)

1.6000

8’hf6

9 (10012)

1.6000

8’hf5

10 (10102)

1.4545

8’hf5

10 (10102)

1.4545

8’hf4

11 (10112)

1.3333

8’hf4

11 (10112)

1.3333

8’hf3

12 (11002)

1.2308

8’hf3

12 (11002)

1.2308

8’hf2

13 (11012)

1.1429

8’hf2

13 (11012)

1.1429

8’hf1

14 (11102)

1.0667

8’hf1

14 (11102)

1.0667

8’hf0

15 (11112)

1.0000

8’hf0

15 (11112)

1.0000

Table 7 : Analogue Gain Settings

STV-DCA/CIF-R01 数据表(PDF) 22 Page - STMicroelectronics

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