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UPD78F9221CS 数据表(PDF) 21 Page - Renesas Technology Corp

部件名 UPD78F9221CS
功能描述  MOS INTEGRATED CIRCUIT
PDF  30 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

UPD78F9221CS 数据表(HTML) 21 Page - Renesas Technology Corp

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Preliminary Product Information U18680EJ1V0PM00
19
µ PD78F9221CS, 78F9222CS
A/D Converter Characteristics (TA =
−40 to +85°C, 2.7 V ≤ AVREF ≤ VDD ≤ 5.5 V, VSS = 0 VNote 1)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Resolution
10
10
10
bit
4.0 V
≤ AVREF ≤ 5.5 V
±0.2
±0.4
%FSR
Overall error
Notes 2, 3
AINL
2.7 V
≤ AVREF < 4.0 V
±0.3
±0.6
%FSR
4.5 V
≤ AVREF ≤ 5.5 V
3.0
100
µs
4.0 V
≤ AVREF < 4.5 V
4.8
100
µs
2.85 V
≤ AVREF < 4.0 V
6.0
100
µs
Conversion time
tCONV
2.7 V
≤ AVREF < 2.85 V
14.0
100
µs
4.0 V
≤ AVREF ≤ 5.5 V
±0.4
%FSR
Zero-scale error
Notes 2, 3
Ezs
2.7 V
≤ AVREF < 4.0 V
±0.6
%FSR
4.0 V
≤ AVREF ≤ 5.5 V
±0.4
%FSR
Full-scale error
Notes 2, 3
Efs
2.7 V
≤ AVREF < 4.0 V
±0.6
%FSR
4.0 V
≤ AVREF ≤ 5.5 V
±2.5
LSB
Integral non-linearity error
Note 2
ILE
2.7 V
≤ AVREF < 4.0 V
±4.5
LSB
4.0 V
≤ AVREF ≤ 5.5 V
±1.5
LSB
Differential non-linearity error
Note 2
DLE
2.7 V
≤ AVREF < 4.0 V
±2.0
LSB
Analog input voltage
VAIN
VSS
Note 1
AVREF
V
Notes 1.
In the 78K0S/KA1+, VSS functions alternately as the ground potential of the A/D converter. Be sure to
connect VSS to a stabilized GND (= 0 V).
2.
Excludes quantization error (
±1/2 LSB).
3.
This value is indicated as a ratio (%FSR) to the full-scale value.
Caution
The conversion accuracy may be degraded when the analog input pin is used as an alternate I/O
port or if a port is changed during A/D conversion.



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