| 数据搜索系统,热门电子元器件搜索 |
|
UPD78P018F 数据表(PDF) 39 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
UPD78P018F 数据表(HTML) 39 Page - Renesas Technology Corp |
|
39 / 78 page ![]() 37 µPD78P018F AC Characteristics (1) Basic Operation (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Cycle time TCY Operating on 3.5 V ≤ VDD ≤ 5.5 V 0.4 64 µs (Min. instruction main system clock 2.7 V ≤ VDD < 3.5 V 0.8 64 µs execution time) 1.8 V ≤ VDD < 2.7 V 2.0 64 µs Operating on subsystem clock 40Note 1 122 125 µs TI0 input tTIH0, 3.5 V ≤ VDD ≤ 5.5 V 2/fsam + 0.1Note 2 µs high-/low-level width tTIL0 2.7 V ≤ VDD < 3.5 V 2/fsam + 0.2Note 2 µs 1.8 V ≤ VDD < 2.7 V 2/fsam + 0.5Note 2 µs TI1, TI2 input fTI1 VDD = 4.5 to 5.5 V 0 4 MHz frequency 0 275 kHz TI1, TI2 input tTIH1,VDD = 4.5 to 5.5 V 100 ns high-/low-level width tTIL1 1.8 µs Interrupt input request tINTH, INTP0 3.5 V ≤ VDD ≤ 5.5 V 2/fsam + 0.1Note 2 µs high-/low-level width tINTL 2.7 V ≤ VDD < 3.5 V 2/fsam + 0.2Note 2 µs 1.8 V ≤ VDD < 2.7 V 2/fsam + 0.5Note 2 µs INTP1 to INTP3, VDD = 2.7 to 5.5 V 10 µs KR0 to KR7 20 µs RESET low-level width tRSL VDD = 2.7 to 5.5 V 10 µs 20 µs Notes 1. Value when using an external clock. When a crystal resonator is used, the value becomes 114 µs (MIN.). 2. In combination with bits 0 (SCS0) and 1 (SCS1) of sampling clock select register (SCS), selection of fsam is possible between fX/2N+1, fX/64, and fX/128 (when N= 0 to 4). |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |