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UPD78P048A 数据表(PDF) 39 Page - Renesas Technology Corp

部件名 UPD78P048A
功能描述  MOS INTEGRATED CIRCUIT
PDF  73 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

UPD78P048A 数据表(HTML) 39 Page - Renesas Technology Corp

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µPD78P048A
37
Data Sheet U10611EJ2V1DS
DC Characteristics (TA = –40 to +85
°C, VDD = 2.7 to 6.0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
High-level
VIH1
P21, P23
0.7 VDD
VDD
V
input voltage
VIH2
P00 to P03, P20, P22, P24 to P27, P33, P34, RESET
0.8 VDD
VDD
V
VIH3
P70 to P74
N-ch open-drain
0.7 VDD
15
V
VIH4
X1, X2
VDD – 0.5
VDD
V
VIH5
XT1/P04, XT2
VDD = 4.5 to 6.0 V
VDD – 0.5
VDD
V
VDD – 0.3
VDD
V
VIH6
P10 to P17, P30 to P32,
VDD = 4.5 to 6.0 V
0.65 VDD
VDD
V
P35 to P37
0.7 VDD
VDD
V
VIH7
P110 to P117, P120 to P127
VDD = 4.5 to 6.0 V
0.7 VDD
VDD
V
VDD – 0.5
VDD
V
Low-level
VIL1
P21, P23
0
0.3 VDD
V
input voltage
VIL2
P00 to P03, P20, P22, P24 to P27, P33, P34, RESET
0
0.2 VDD
V
VIL3
P70 to P74
VDD = 4.5 to 6.0 V
0
0.3 VDD
V
0
0.2 VDD
V
VIL4
X1, X2
0
0.4
V
VIL5
XT1/P04, XT2
VDD = 4.5 to 6.0 V
0
0.4
V
0
0.3
V
VIL6
P10 to P17, P30 to P32, P35 to P37 VDD = 4.5 to 6.0 V
0
0.3 VDD
V
VIL7
P110 to P117, P120 to P127
VDD – 3.5
0.3 VDD
V
High-level
VOH
VDD = 4.5 to 6.0 V,
VDD – 1.0
V
output voltage
IOH = –1 mA
IOH = –100
µA
VDD – 0.5
V
Low-level
VOL1
P30 to P37, P70 to P74
VDD = 4.5 to 6.0 V
0.4
2.0
V
output voltage
IOL = 15 mA
P01 to P03, P10 to P17,
VDD = 4.5 to 6.0 V
0.4
V
P20 to P27
IOL = 1.6 mA
VOL2
SB0, SB1, SCK0
VDD = 4.5 to 6.0 V
0.2 VDD
V
With open-drain and
pull-up (R = 1 k
Ω)
VOL3
P01 to P03, P10 to P17, P20 to IOL = 400
µA
0.5
V
P27, P30 to P37, P70 to P74
High-level
ILIH1
VIN = VDD
P00 to P03, P10 to P17,
3
µA
input leakage
P20 to P27, P30 to P37,
current
RESET
ILIH2
X1, X2, XT1/P04, XT2
20
µA
ILIH3
VIN = 15 V
P70 to P74
20
µA
ILIH4
P110 to P117, P120 to P127
VDD = 4.5 to 6.0 V
3Note 1
µA
VIN = VDD
3Note 2
µA
Notes 1. For P110 to P117 and P120 to P127, a high-level input leak current of 150
µA (MAX.) flows only during
the 1.5 clocks after an instruction has been executed to read out ports 11, 12 (P11, 12) or port mode
registers 11, 12 (PM11, 12). Outside the period of 1.5 clocks following executing a read-out instruction,
the current is 3
µA (MAX.).
2. For P110 to P117 and P120 to P127, a high-level input leak current of 90
µA (MAX.) flows only during the
1.5 clocks after an instruction has been executed to read out P11, P12, PM11, and PM12. Outside the
period of 1.5 clocks following executing a read-out instruction, the current is 3
µA (MAX.).
Remark Unless otherwise specified, the characteristics of a shared pin are the same as those of a port pin.
P01 to P03, P10 to P17, P20 to
P27, P30 to P37, P80, P81, P90
to P97, P100 to P107, P110 to
P117, P120 to P127



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