2000 January

3

Philips Semiconductors

Product specification

Frame Transfer CCD Image Sensor

FT 18

Architecture of the FT 18

The FT18 consists of a shielded storage section and an open image

section. Both sections have the same structure with identical cells

and properties. The only difference between the two sections is the

optical light shield.

The optical centres of all pixels in the image section form a square

grid. The charge is generated and integrated in this section. The

image section is controlled by four image clocks (A1 to A4). After

integration, the image charge is completely shifted to the storage

section. The integration time is electronically controlled by charge

reset (CR).

The storage section is controlled by four storage clocks (B1 to B4).

An output register is located below the storage section for read-out.

The output register has buffers at both ends. This allows either normal

or mirrored read-out.

Transport of the pixels in the output register is controlled by three

register clock phases (C1 to C3).The register can be used for vertical

binning. Horizontal binning can be achieved by summing pixel

charges under the floating diffusion. More information can be found

in the application note. Figure 2 shows the detailed internal structure.

IMAGE SECTION

Image diagonal

Aspect ratio

Active image width x height

Total width x height

Pixel width x height

Geometric fill factor

Image clock pins

Capacity of each clock phase

Number of active lines

Number of contour lines

Number of black lines

Total number of lines

Number of active pixels per line

Number of overscan (timing) pixels per line

Number of black reference pixels per line

Total number of pixels per line

10.9 mm

1:1

7.680 x 7.680 mm

2

8.040 x 7.860 mm

2

7.5 x 7.5 µm

2

100%

A1, A2, A3, A4

<3.75nF per pin

1024

4 (top) + 1 (bottom)

8 (top) + 11 (bottom)

1048

1024

8 (2x4)

40 (2x20)

1072

STORAGE SECTION

Storage width x height

Cell width x height

Storage clock phases

Capacity of each B phase

Number of cells per line x number of lines

8.040 x 7.860 mm

2

7.5 x 7.5 µm

2

B1, B2, B3, B4

<4.1nF per pin

1072 x 1048

OUTPUT REGISTER

Output buffers (three-stage source follower)

Number of registers

Number of register cells below storage

Number of extra cells to output

Output register horizontal transport clock pins

Capacity of each C-clock phase

Overlap capacity between neighbouring C-clocks

Reset Gate clock phases

Capacity of each RG

2

1 (bidirectional below storage)

1072

2 x 7

3 (C1..C3)

<85pF per pin

<35pF

2 pins (RGL, RGR)

<15pF