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M24C64-R 数据表(PDF) 25 Page - STMicroelectronics

部件名 M24C64-R
功能描述  128 Kbit, 64 Kbit and 32 Kbit serial I2C bus EEPROM
PDF  34 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

M24C64-R 数据表(HTML) 25 Page - STMicroelectronics

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M24128, M24C64, M24C32
DC and AC parameters
25/34
Table 17.
AC characteristics (VCC = 2.5V to 5.5V, device grades 6 and 3)
Test conditions specified in Table 11 and Table 8
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
fSCL
Clock Frequency
400
kHz
tCHCL
tHIGH
Clock Pulse Width High
600
ns
tCLCH
tLOW
Clock Pulse Width Low
1300
ns
tDL1DL2
(1)
1.
Sampled only, not 100% tested.
tF
SDA Fall Time
20
300
ns
tDXCX
tSU:DAT Data In Set Up Time
100
ns
tCLDX
tHD:DAT Data In Hold Time
0
ns
tCLQX
tDH
Data Out Hold Time
200
ns
tCLQV
(2)
2.
To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the
falling or rising edge of SDA.
tAA
Clock Low to Next Data Valid (Access Time)
200
900
ns
tCHDX
(3)
3.
For a reSTART condition, or following a Write cycle.
tSU:STA Start Condition Set Up Time
600
ns
tDLCL
tHD:STA Start Condition Hold Time
600
ns
tCHDH
tSU:STO Stop Condition Set Up Time
600
ns
tDHDL
tBUF
Time between Stop Condition and Next Start Condition
1300
ns
tW
tWR
Write Time
5
ms
Table 18.
AC characteristics (VCC = 1.8V to 5.5V or VCC = 1.7V to 5.5V)
Test conditions specified in Table 11 and Table 9 or Table 10
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
fSCL
Clock Frequency
400
kHz
tCHCL
tHIGH
Clock Pulse Width High
600
ns
tCLCH
tLOW
Clock Pulse Width Low
1300
ns
tDL1DL2
(1)
1.
Sampled only, not 100% tested.
tF
SDA Fall Time
20
300
ns
tDXCX
tSU:DAT Data In Set Up Time
100
ns
tCLDX
tHD:DAT Data In Hold Time
0
ns
tCLQX
tDH
Data Out Hold Time
200
ns
tCLQV
(2)
2.
To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the
falling or rising edge of SDA.
tAA
Clock Low to Next Data Valid (Access Time)
200
900
ns
tCHDX
(3)
3.
For a reSTART condition, or following a Write cycle.
tSU:STA Start Condition Set Up Time
600
ns
tDLCL
tHD:STA Start Condition Hold Time
600
ns
tCHDH
tSU:STO Stop Condition Set Up Time
600
ns
tDHDL
tBUF
Time between Stop Condition and Next Start Condition
1300
ns
tW
tWR
Write Time
10
ms



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