1/14

July 2001

s

HIGH SPEED :

s

LOW POWER DISSIPATION:

s

HIGH NOISE IMMUNITY:

s

SYMMETRICAL OUTPUT IMPEDANCE:

s

BALANCED PROPAGATION DELAYS:

s

WIDE OPERATING VOLTAGE RANGE:

s

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 192

DESCRIPTION

The

M74HC192

is

an

high

speed

CMOS

SYNCRONOUS

UP/DOWN

DECADE

technology.

The counter has two separate clock inputs, an UP

COUNT input and a DOWN COUNT input. All

outputs

of

the

flip-flop

are

simultaneously

triggered on the low to high transition of either

clock while the other input is held high. The

direction of counting is determined by which input

is clocked. This counter may be preset by entering

the desired data on the DATA A, DATA B, DATA

C, and DATA D input. When the LOAD input is

taken low the data is loaded independently of

either clock input. This feature allows the counters

to be used as divide-by-n counters by modifying

the count length with the preset inputs. In addition

the

counter

can

also

be

cleared.

This

is

accomplished by inputting a high on the CLEAR

input. All 4 internal stages are set to low

independently of either COUNT input. Both a

BORROW and CARRY output are provided to

enable cascading of both up and down counting

functions. The BORROW output produces a

negative going pulse when the counter underflows

and the CARRY outputs a pulse when the

counters overflows. The counter can be cascaded

by connection the CARRY and BORROW outputs

of one device to the COUNT UP and COUNT

DOWN inputs, respectively, of the next device.

All inputs are equipped with protection circuits

against static discharge and transient excess

voltage.

M74HC192

SYNCHRONOUS UP/DOWN DECADE COUNTER

PIN CONNECTION AND IEC LOGIC SYMBOLS

ORDER CODES

PACKAGE

TUBE

T & R

DIP

M74HC192B1R

SOP

M74HC192M1R

M74HC192RM13TR

TSSOP

M74HC192TTR

TSSOP

DIP

SOP