HY5V26C(L/S)F

Rev. 0.9/Jul. 02

8

Note :

1.Assume tR / tF (input rise and fall time ) is 1ns

If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter

2.Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v

If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter

Parameter

Symbol

-6

-K

-H

-8

-P

-S

Unit

Note

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

System Clock Cycle

Time

CAS Latency = 3

tCK3

6

1000

7.5

1000

7.5

1000

8

1000

10

1000

10

1000

ns

CAS Latency = 2

tCK2

10

7.5

10

10

10

12

ns

Clock High Pulse Width

tCHW

2.5

-

2.5

-

2.5

-

3

-

3

-

3

-

ns

1

Clock Low Pulse Width

tCLW

2.5

-

2.5

-

2.5

-

3

-

3

-

3

-

ns

1

Access Time From

Clock

CAS Latency = 3

tAC3

-

5.4

-

5.4

-

5.4

-

6

-

6

-

6

ns

2

CAS Latency = 2

tAC2

-

6

-

5.4

-

6

-

6

-

6

-

6

ns

Data-Out Hold Time

tOH

2.7

-

2.7

-

2.7

-

3

-

3

-

3

-

ns

Data-Input Setup Time

tDS

1.5

-

1.5

-

1.5

-

2

-

2

-

2

-

ns

1

Data-Input Hold Time

tDH

0.8

-

0.8

-

0.8

-

1

-

1

-

1

-

ns

1

Address Setup Time

tAS

1.5

-

1.5

-

1.5

-

2

-

2

-

2

-

ns

1

Address Hold Time

tAH

0.8

-

0.8

-

0.8

-

1

-

1

-

1

-

ns

1

CKE Setup Time

tCKS

1.5

-

1.5

-

1.5

-

2

-

2

-

2

-

ns

1

CKE Hold Time

tCKH

0.8

-

0.8

-

0.8

-

1

-

1

-

1

-

ns

1

Command Setup Time

tCS

1.5

-

1.5

-

1.5

-

2

-

2

-

2

-

ns

1

Command Hold Time

tCH

0.8

-

0.8

-

0.8

-

1

-

1

-

1

-

ns

1

CLK to Data Output in Low-Z Time

tOLZ

1-1-

1-

1

-

1-1-

ns

CLK to Data Output

in High-Z Time

CAS Latency = 3

tOHZ3

2.7

5.4

2.7

5.4

2.7

5.4

3

6

3

6

3

6

ns

CAS Latency = 2

tOHZ2

2.7

5.4

2.7

5.4

3

6

3

6

3

6

3

6

ns