HY5V26C(L/S)F

BALL DESCRIPTION

BALL OUT

SYMBOL

TYPE

DESCRIPTION

F2

CLK

INPUT

Clock : The system clock input. All other inputs are registered to the

SDRAM on the rising edge of CLK

F3

CKE

INPUT

Clock Enable : Controls internal clock signal and when deactivated,

the SDRAM will be one of the states among power down, suspend or

self refresh

G9

CS

INPUT

Chip Select : Enables or disables all inputs except CLK, CKE, UDQM

and LDQM

G7,G8

BA0, BA1

INPUT

Bank Address : Selects bank to be activated during RAS activity

Selects bank to be read/written during CAS activity

H7, H8, J8, J7,

J3, J2, H3, H2,

H1, G3, H9, G2

A0 ~ A11

INPUT

Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8

Auto-precharge flag : A10

F8, F7, F9

RAS, CAS,

WE

INPUT

Command Inputs : RAS, CAS and WE define the operation

Refer function truth table for details

F1, E8

UDQM,

LDQM

INPUT

Data Mask:Controls output buffers in read mode and masks input

data in write mode

A8, B9, B8, C9,

C8, D9, D8, E9,

E1, D2, D1, C2,

C1, B2, B1, A2

DQ0 ~ DQ15

I/O

Data Input/Output:Multiplexed data input/output ball

A9, E7, J9, A1,

E3, J1

VDD/VSS

SUPPLY

Power supply for internal circuits

A7, B3, C7, D3,

A3, B7, C3, D7

VDDQ/VSSQ SUPPLY

Power supply for output buffers

E2, G1

NC

-

No connection