Data Sheet S12581EJ1V0DS00

11

µµµµ PD16640B

Switching Characteristics (TA = –10 to +75

°C, VDD1 = 3.3 V ±±±± 0.3 V, VDD2 = 3.3 V ±±±± 0.3 V or 5.0 V ±±±± 0.5 V,

VSS1 = VSS2 = 0 V)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

tPLH1

CL = 15 pF

12

ns

Start Pulse Delay time

tPHL1

12

ns

Driver Output Delay Time

tPLH21

VDD2 = 3.3 V,

VO: 0.1 V

→ 3.2 V

3.3

µ s

tPLH31

4 k

Ω +24 pF × 25.1

10

µ s

tPHL21

VO: 3.2 V

→ 0.1 V

4.3

µ s

tPHL31

5.4

10

µ s

tPLH22

VDD2 = 5.0 V,

VO: 0.1 V

→ 4.9 V

4.2

µ s

tPLH32

4 k

Ω +24 pF × 25.4

10

µ s

tPHL22

VO: 4.9 V

→ 0.1 V

4.9

µ s

tPHL32

6.2

10

µ s

Input capacitance

CI1

STHR (STHL), TA = 25

°C10

15

pF

CI2

V0 to V10, TA = 25

°C

100

pF

CI3

STHR (STHL), other than V0 to V10,

5

10

pF

TA = 25

°C

Timing Requirements (TA = –10 to +75

°C, VDD1 = 3.3 V ±±±± 0.3 V, VDD2 = 3.3 V ±±±± 0.3 V or 5.0 V ±±±± 0.5 V,

VSS1 = VSS2 = 0 V)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

Clock Pulse Width

PWCLK

18

ns

Clock Pulse High Period

PWCLK (H)

4ns

Clock Pulse Low Period

PWCLK (L)

4ns

Data Setup Time

tSETUP1

4ns

Data Hold Time

tHOLD1

0ns

Start Pulse Setup Time

tSETUP2

4ns

Start Pulse Hold Time

tHOLD2

0ns

INV Setup time

tSETUP4

4ns

INV Hold time

tHOLD4

0ns

Start Pulse Low period

tSPL

2CLK

Start Pulse Rise Time

tSPR1

Osel = H

100

CLK

Start Pulse Rise Time

tSPR2

Osel = L

103

CLK

STB setup time

tSETUP3

2CLK

Data Invalid Period

tINV

1CLK

Last Data Timing

tLDT

1CLK

CLK-STB Time

tCLK-STB

CLK

↑ → STB ↑ or ↓

7ns

STB-CLK Time

tSTB-CLK

STB

↑ or ↓ → CLK ↑

7ns