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UPD17062 数据表(PDF) 82 Page - Renesas Technology Corp

部件名 UPD17062
功能描述  MOS INTEGRATED CIRCUIT
PDF  298 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

UPD17062 数据表(HTML) 82 Page - Renesas Technology Corp

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µPD17062
9.11
TIMER CARRY (17H)
9.12
SERIAL INTERFACE WAIT CONTROL (18H)
9.13
IEGNC (1FH)
The IEGNC flag is used for selecting the interrupt detection edge of the INTNC pin and VSYNC pin.
When the flag is set to 0, an interrupt occurs at a rising edge. When the flag is set to 1, an interrupt occurs
at a falling edge.
b3
b2
b1
b0
17H
Exclusive flag for reading timer carry
00
0
BTM0CY
This flag is set according to the selected time base,
and reset when the timer carry is read.
b3
b2
b1
b0
18H
Setting of wait timing
0
1
SBACK
SIO0NWT
SIO0WRQ1 SIO0WRQ0
00
01
10
11
2-wire bus mode
Serial I/O mode
Does not wait
Does not wait
Waits when the clock falls with the contents
of the clock counter being 8
Waits when the clock falls with the contents
of the clock counter being 9
Waits when the clock falls with the contents
of the clock counter being 8 after detection
of the start condition
Waits when the contents of the
clock counter become 9
Waits when the contents of the
clock counter become 9
Not to be set
Wait setting
Acknowledgement at 2-wire bus mode
Forced wait
Wait released
b3
b2
b1
b0
0
IEGVSYN
IEGNC
1FH
0
0
1
0
1
Interrupt occurs at the rising edge of the VSYNC pin
Interrupt occurs at the falling edge of the VSYNC pin
Interrupt occurs at the rising edge of the INTNC pin
Interrupt occurs at the falling edge of the INTNC pin



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