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HCS320 数据表(PDF) 11 Page - Microchip Technology |
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HCS320 数据表(HTML) 11 Page - Microchip Technology |
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11 / 28 page  2004 Microchip Technology Inc. Preliminary DS41256A-page 11 HCSXXX 2.4 Bulk Write Device All transponders and encoders are bulk erased and programmed with zeros following the Start condition. The bulk erase/write time frame is specified as TPBW, which is minimally 4.0 ms. After the bulk function is complete, the programming state machine continues into the Program mode where it begins to wait for data and clock signals. 2.5 Serial Program/Verify Operation For all of the encoders and transponders, the memory maps have been designed to be in 16-bit format, which means that each address location contains 16 bits of information including “don't care” bits that are read as zeros. Details relating to the designated pins for clock and data signals are outlined in Table 1-1. The decoders, on the other hand, were designed with memory maps in 8-bit format, so they are discussed separately in the next couple of paragraphs. For specific information relating to the size of the memory maps for a given family of devices, be sure to review the tables in Section 2.1 “Encoder Memory Maps”. The following paragraphs were written with the assumption that the target device has been placed into the Programming mode and is now waiting for data or a command byte to continue programming the memory array. 2.5.1 ENCODERS/TRANSPONDERS To input data to the target KEELOQ encoder or transponder, 16 clock cycles are applied to the clock pin of the target device while data is driven into the data pin. Data is clocked into the target device on the falling edge of the clock signal. Also, the minimum high time and low time for the clock signals are 50 µs. During verification, data must be sampled on the rising edge of the clock. 2.5.2 DECODERS To input data to the target KEELOQ decoder, 8 clock cycles are applied to the clock pin of the target device while data is driven into the data pin. Data is clocked into the target device on the falling edge of the clock signals. Also, the minimum high time and minimum low time for the clock signals are 50 µs. For the decoder family, there are no verification functions. 2.6 Begin Programming Write cycles are performed a bit-at-a-time throughout the entire programming sequence for KEELOQ products. The total write cycle, which includes internal processing and programming time, is specified to take a minimum of 50 ms. As a result, programmers can include a delay for the minimum write cycle time or they can poll the target device as discussed in Section 2.7 “Polling Write Cycle”. 2.7 Polling Write Cycle 2.7.1 HCS201 AND HCS412 Once the 16th clock cycle for the data word has been generated and the next minimum low time for the clock passes, the clock pin can be driven high to poll the completion of the write cycle. Before the write cycle is complete, the data pin for the target KEELOQ device will be low. After the write cycle is complete, the data pin on the HCS201 and the HCS412 will begin to provide pulses to the programmer in order to signal the completion of the write cycle. As a result, the programmer data pin should be set to high-impedance (input) so that it can read the pulses. After reading the pulses on the data pin, the programmer should drive the clock pin low and make the data pin an output so that data can continue to be driven into the target device. These pulses can be used for calibration sequences for the HCS201 and the HCS412. For information relating to oscillator calibration refer to Section 5.0 “Program/Verify Mode Electrical Characteristics”, which discusses oscillator tuning. If the programmer polls the target device for the end of a write cycle, these two devices will continue to emit calibration pulses until their clock lines are driven low. In order to measure the calibration pulses, the clock pin must be driven high prior to the end of the write cycle, otherwise the calibration pulses will not appear. 2.7.2 ALL OTHER KEELOQ DEVICES Once the 16th clock cycle for the data word has been generated for any of the encoders or transponders or the last clock cycle for a decoder data packet is generated, the clock pin can be driven high to poll for the completion of the write cycle. Before the write cycle is complete, the data pin for the target KEELOQ device will be low. As a result, the programmer data pin should be set to high-impedance (input) so that it can sense the rising edge of data. After the write cycle is complete, the data pin will be driven high until the clock line is driven low again. |
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